Low noise 0.9 GHz FBAR clock

Markku Åberg; Miikka Ylimaula; Markku Ylilammi; Tuomas Pensala; Arto Rantala

doi:10.1109/NORCHP.2005.1597038

Low noise 0.9 GHz FBAR clock

Markku Åberg, Miikka Ylimaula, Markku Ylilammi, Tuomas Pensala, Arto Rantala

VTT (former employee or external)

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

A low noise 0.9GHz FBAR clock consisting of an oscillator and divider circuit for single sided-to-differential conversion for high-speed A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 /spl mu/m CMOS process, and tested. The circuit showed very good jitter and phase noise performance.

Original language	English
Title of host publication	2005 NORCHIP
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	257-260
ISBN (Print)	978-1-4244-0064-5
DOIs	https://doi.org/10.1109/NORCHP.2005.1597038
Publication status	Published - 2005
MoE publication type	A4 Article in a conference publication
Event	23rd Norchip Conference, IEEE NORCHIP 2005 - Oulu, Finland Duration: 21 Nov 2005 → 22 Nov 2005

Conference

Conference	23rd Norchip Conference, IEEE NORCHIP 2005
Country/Territory	Finland
City	Oulu
Period	21/11/05 → 22/11/05

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10.1109/NORCHP.2005.1597038

Cite this

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title = "Low noise 0.9 GHz FBAR clock",

abstract = "A low noise 0.9GHz FBAR clock consisting of an oscillator and divider circuit for single sided-to-differential conversion for high-speed A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 /spl mu/m CMOS process, and tested. The circuit showed very good jitter and phase noise performance.",

author = "Markku {\AA}berg and Miikka Ylimaula and Markku Ylilammi and Tuomas Pensala and Arto Rantala",

year = "2005",

doi = "10.1109/NORCHP.2005.1597038",

language = "English",

isbn = "978-1-4244-0064-5",

pages = "257--260",

booktitle = "2005 NORCHIP",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "23rd Norchip Conference, IEEE NORCHIP 2005 ; Conference date: 21-11-2005 Through 22-11-2005",

}

TY - GEN

T1 - Low noise 0.9 GHz FBAR clock

AU - Åberg, Markku

AU - Ylimaula, Miikka

AU - Ylilammi, Markku

AU - Pensala, Tuomas

AU - Rantala, Arto

PY - 2005

Y1 - 2005

N2 - A low noise 0.9GHz FBAR clock consisting of an oscillator and divider circuit for single sided-to-differential conversion for high-speed A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 /spl mu/m CMOS process, and tested. The circuit showed very good jitter and phase noise performance.

AB - A low noise 0.9GHz FBAR clock consisting of an oscillator and divider circuit for single sided-to-differential conversion for high-speed A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 /spl mu/m CMOS process, and tested. The circuit showed very good jitter and phase noise performance.

U2 - 10.1109/NORCHP.2005.1597038

DO - 10.1109/NORCHP.2005.1597038

M3 - Conference article in proceedings

SN - 978-1-4244-0064-5

SP - 257

EP - 260

BT - 2005 NORCHIP

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 23rd Norchip Conference, IEEE NORCHIP 2005

Y2 - 21 November 2005 through 22 November 2005

ER -

Low noise 0.9 GHz FBAR clock

Abstract

Conference

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