Low power high-speed neuron MOS digital-to-analog converters with minimal silicon area

Arto Rantala, Pekka Kuivalainen, Markku Åberg

Research output: Contribution to journalArticleScientificpeer-review

1 Citation (Scopus)

Abstract

Digital-to-analog converts utilizing neuron MOS-transistors were designed. Different DACs were implemented and characterized in order to compare various topologies. Criteria to select structures were low power, fast performance and minimal silicon area. A basic 8-bit version is implemented with only one neuron MOS-transistor and eight capacitors. The silicon area of this D/A converter is only 0.04 mm2 and the power consumption is 8.4 mW with conversion speed of 200 MS/s. An enhanced 8 and 10 bit versions utilizing neuron PMOS transistor and some extra circuitry are also proposed and tested. The silicon area of the enhanced 10 bit circuit is only 0.03mm2 while the performance is as good as in the case of the basic version. The measured differential nonlinearity is 0.38 LSB and integral nonlinearity is 0.55 LSB for the enhanced 10 bit structure.
Original languageEnglish
Pages (from-to)53-62
Number of pages10
JournalAnalog Integrated Circuits and Signal Processing
Volume26
Issue number1
DOIs
Publication statusPublished - 2001
MoE publication typeA1 Journal article-refereed

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Silicon
Digital to analog conversion
Neurons
MOSFET devices
Transistors
Electric power utilization
Capacitors
Topology
Networks (circuits)

Cite this

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title = "Low power high-speed neuron MOS digital-to-analog converters with minimal silicon area",
abstract = "Digital-to-analog converts utilizing neuron MOS-transistors were designed. Different DACs were implemented and characterized in order to compare various topologies. Criteria to select structures were low power, fast performance and minimal silicon area. A basic 8-bit version is implemented with only one neuron MOS-transistor and eight capacitors. The silicon area of this D/A converter is only 0.04 mm2 and the power consumption is 8.4 mW with conversion speed of 200 MS/s. An enhanced 8 and 10 bit versions utilizing neuron PMOS transistor and some extra circuitry are also proposed and tested. The silicon area of the enhanced 10 bit circuit is only 0.03mm2 while the performance is as good as in the case of the basic version. The measured differential nonlinearity is 0.38 LSB and integral nonlinearity is 0.55 LSB for the enhanced 10 bit structure.",
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Low power high-speed neuron MOS digital-to-analog converters with minimal silicon area. / Rantala, Arto; Kuivalainen, Pekka; Åberg, Markku.

In: Analog Integrated Circuits and Signal Processing, Vol. 26, No. 1, 2001, p. 53-62.

Research output: Contribution to journalArticleScientificpeer-review

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