Mappability estimate: a measure of the goodness of a processor-algorithm pair

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    Abstract

    A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.
    Original languageEnglish
    Title of host publicationProceedings, 2003 International Symposium on System-on-Chip
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages119 -122
    ISBN (Print)0-7803-8160-2
    DOIs
    Publication statusPublished - 2003
    MoE publication typeA4 Article in a conference publication
    Event2003 International Symposium on System-on-Chip - Tampere, Finland
    Duration: 19 Nov 200321 Nov 2003

    Conference

    Conference2003 International Symposium on System-on-Chip
    CountryFinland
    CityTampere
    Period19/11/0321/11/03

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