Mappability estimate: a measure of the goodness of a processor-algorithm pair

Jari Kreku; Juha-Pekka Soininen

doi:10.1109/ISSOC.2003.1267731

Mappability estimate: a measure of the goodness of a processor-algorithm pair

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

1 Citation (Scopus)

Abstract

A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.

Original language	English
Title of host publication	Proceedings, 2003 International Symposium on System-on-Chip
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	119-122
ISBN (Print)	978-0-7803-8160-5
DOIs	https://doi.org/10.1109/ISSOC.2003.1267731
Publication status	Published - 2003
MoE publication type	A4 Article in a conference publication
Event	2003 International Symposium on System-on-Chip - Tampere, Finland Duration: 19 Nov 2003 → 21 Nov 2003

Conference

Conference	2003 International Symposium on System-on-Chip
Country/Territory	Finland
City	Tampere
Period	19/11/03 → 21/11/03

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10.1109/ISSOC.2003.1267731

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title = "Mappability estimate: a measure of the goodness of a processor-algorithm pair",

abstract = "A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.",

author = "Jari Kreku and Juha-Pekka Soininen",

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doi = "10.1109/ISSOC.2003.1267731",

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booktitle = "Proceedings, 2003 International Symposium on System-on-Chip",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "2003 International Symposium on System-on-Chip ; Conference date: 19-11-2003 Through 21-11-2003",

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Mappability estimate: a measure of the goodness of a processor-algorithm pair. / Kreku, Jari; Soininen, Juha-Pekka.
Proceedings, 2003 International Symposium on System-on-Chip. IEEE Institute of Electrical and Electronic Engineers, 2003. p. 119-122.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Mappability estimate: a measure of the goodness of a processor-algorithm pair

AU - Kreku, Jari

AU - Soininen, Juha-Pekka

PY - 2003

Y1 - 2003

N2 - A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.

AB - A quick way of measuring the goodness of a processor-algorithm pair is presented. The main emphasis in this paper is in the reasoning of the mappability factors of a processor and an algorithm. Typical algorithm properties and how they affect the usability of the corresponding architecture characteristics are considered. The mappability estimation approach is demonstrated using MiBench benchmark algorithms and the Simplescalar processor simulator with ARM instruction set. The estimation results are consistent with the simulations and the estimates correctly predicted the most suitable architectures for three of the four algorithms.

U2 - 10.1109/ISSOC.2003.1267731

DO - 10.1109/ISSOC.2003.1267731

M3 - Conference article in proceedings

SN - 978-0-7803-8160-5

SP - 119

EP - 122

BT - Proceedings, 2003 International Symposium on System-on-Chip

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 2003 International Symposium on System-on-Chip

Y2 - 19 November 2003 through 21 November 2003

ER -

Mappability estimate: a measure of the goodness of a processor-algorithm pair

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