Mappability estimation of architecture and algorithm

Juha-Pekka Soininen; Jari Kreku; Yang Qu

doi:10.1109/DATE.2002.998488

Mappability estimation of architecture and algorithm

Juha-Pekka Soininen, Jari Kreku, Yang Qu

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific

1 Citation (Scopus)

Abstract

Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations.

Original language	English
Title of host publication	Proceedings 2002, Design, Automation and Test in Europe Conference and Exhibition, DATE 2002
Subtitle of host publication	Paris, France, 4-8 March 2002
Publisher	IEEE Institute of Electrical and Electronic Engineers
ISBN (Print)	0-7695-1471-5
DOIs	https://doi.org/10.1109/DATE.2002.998488
Publication status	Published - 2002
MoE publication type	B3 Non-refereed article in conference proceedings

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10.1109/DATE.2002.998488

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title = "Mappability estimation of architecture and algorithm",

abstract = "Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations.",

author = "Juha-Pekka Soininen and Jari Kreku and Yang Qu",

note = "Project code: MULTICS",

year = "2002",

doi = "10.1109/DATE.2002.998488",

language = "English",

isbn = "0-7695-1471-5",

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publisher = "IEEE Institute of Electrical and Electronic Engineers",

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Mappability estimation of architecture and algorithm. / Soininen, Juha-Pekka; Kreku, Jari; Qu, Yang.
Proceedings 2002, Design, Automation and Test in Europe Conference and Exhibition, DATE 2002: Paris, France, 4-8 March 2002. IEEE Institute of Electrical and Electronic Engineers, 2002. 1132.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific

TY - GEN

T1 - Mappability estimation of architecture and algorithm

AU - Soininen, Juha-Pekka

AU - Kreku, Jari

AU - Qu, Yang

N1 - Project code: MULTICS

PY - 2002

Y1 - 2002

N2 - Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations.

AB - Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations.

U2 - 10.1109/DATE.2002.998488

DO - 10.1109/DATE.2002.998488

M3 - Conference article in proceedings

SN - 0-7695-1471-5

BT - Proceedings 2002, Design, Automation and Test in Europe Conference and Exhibition, DATE 2002

PB - IEEE Institute of Electrical and Electronic Engineers

ER -

Mappability estimation of architecture and algorithm

Abstract

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