Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations.
|Title of host publication||Proceedings 2002, Design, Automation and Test in Europe Conference and Exhibition, DATE 2002|
|Subtitle of host publication||Paris, France, 4-8 March 2002|
|Publisher||IEEE Institute of Electrical and Electronic Engineers|
|Publication status||Published - 2002|
|MoE publication type||B3 Non-refereed article in conference proceedings|
Soininen, J-P., Kreku, J., & Qu, Y. (2002). Mappability estimation of architecture and algorithm. In Proceedings 2002, Design, Automation and Test in Europe Conference and Exhibition, DATE 2002: Paris, France, 4-8 March 2002  IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/DATE.2002.998488