Mappability estimation of architecture and algorithm

Juha-Pekka Soininen, Jari Kreku, Yang Qu

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific

    1 Citation (Scopus)

    Abstract

    Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations.
    Original languageEnglish
    Title of host publicationProceedings 2002, Design, Automation and Test in Europe Conference and Exhibition, DATE 2002
    Subtitle of host publicationParis, France, 4-8 March 2002
    PublisherIEEE Institute of Electrical and Electronic Engineers
    ISBN (Print)0-7695-1471-5
    DOIs
    Publication statusPublished - 2002
    MoE publication typeB3 Non-refereed article in conference proceedings

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  • Cite this

    Soininen, J-P., Kreku, J., & Qu, Y. (2002). Mappability estimation of architecture and algorithm. In Proceedings 2002, Design, Automation and Test in Europe Conference and Exhibition, DATE 2002: Paris, France, 4-8 March 2002 [1132] IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/DATE.2002.998488