Mapping Optimisation for Scalable Multi-core ARchiTecture

The MOSART Approach

P. Candaele, S. Aguirre, M. Sarlotte, I. Anagnostopoulos, S. Xydis, A. Bartzas, D. Bekiaris, D. Soudris, Zhonghai Lu, Xiaowen Chen, J. Chabloz, A. Hemani, A. Jantsch, G. Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, F. Ieromnimon, D. Kritharidis, A. Wiefrink, B. Vanthournout & 1 others P. Martin

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)
Original languageEnglish
Title of host publicationProceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)
Place of PublicationLos Alamitos, CA, USA
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages518-523
ISBN (Electronic)978-1-4244-7320-5
ISBN (Print)978-1-4244-7321-2
DOIs
Publication statusPublished - 2010
MoE publication typeA4 Article in a conference publication
EventIEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI) - Lixouri, Kefalonia, Greece
Duration: 5 Jul 20107 Jul 2010

Conference

ConferenceIEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)
Abbreviated titleVLSI 2010
CountryGreece
CityLixouri, Kefalonia
Period5/07/107/07/10

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Data storage equipment
Data structures
Communication
Processing
Middleware
Managers
Electric power utilization
Costs
Network-on-chip

Cite this

Candaele, P., Aguirre, S., Sarlotte, M., Anagnostopoulos, I., Xydis, S., Bartzas, A., ... Martin, P. (2010). Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI) (pp. 518-523). Los Alamitos, CA, USA: Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/ISVLSI.2010.71
Candaele, P. ; Aguirre, S. ; Sarlotte, M. ; Anagnostopoulos, I. ; Xydis, S. ; Bartzas, A. ; Bekiaris, D. ; Soudris, D. ; Lu, Zhonghai ; Chen, Xiaowen ; Chabloz, J. ; Hemani, A. ; Jantsch, A. ; Vanmeerbeeck, G. ; Kreku, Jari ; Tiensyrjä, Kari ; Ieromnimon, F. ; Kritharidis, D. ; Wiefrink, A. ; Vanthournout, B. ; Martin, P. / Mapping Optimisation for Scalable Multi-core ARchiTecture : The MOSART Approach. Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI). Los Alamitos, CA, USA : Institute of Electrical and Electronic Engineers IEEE, 2010. pp. 518-523
@inproceedings{65b103d9e26a46be8c6e805e47c87fbc,
title = "Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach",
abstract = "The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)",
author = "P. Candaele and S. Aguirre and M. Sarlotte and I. Anagnostopoulos and S. Xydis and A. Bartzas and D. Bekiaris and D. Soudris and Zhonghai Lu and Xiaowen Chen and J. Chabloz and A. Hemani and A. Jantsch and G. Vanmeerbeeck and Jari Kreku and Kari Tiensyrj{\"a} and F. Ieromnimon and D. Kritharidis and A. Wiefrink and B. Vanthournout and P. Martin",
year = "2010",
doi = "10.1109/ISVLSI.2010.71",
language = "English",
isbn = "978-1-4244-7321-2",
pages = "518--523",
booktitle = "Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)",
publisher = "Institute of Electrical and Electronic Engineers IEEE",
address = "United States",

}

Candaele, P, Aguirre, S, Sarlotte, M, Anagnostopoulos, I, Xydis, S, Bartzas, A, Bekiaris, D, Soudris, D, Lu, Z, Chen, X, Chabloz, J, Hemani, A, Jantsch, A, Vanmeerbeeck, G, Kreku, J, Tiensyrjä, K, Ieromnimon, F, Kritharidis, D, Wiefrink, A, Vanthournout, B & Martin, P 2010, Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. in Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI). Institute of Electrical and Electronic Engineers IEEE, Los Alamitos, CA, USA, pp. 518-523, IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI), Lixouri, Kefalonia, Greece, 5/07/10. https://doi.org/10.1109/ISVLSI.2010.71

Mapping Optimisation for Scalable Multi-core ARchiTecture : The MOSART Approach. / Candaele, P.; Aguirre, S.; Sarlotte, M.; Anagnostopoulos, I.; Xydis, S.; Bartzas, A.; Bekiaris, D.; Soudris, D.; Lu, Zhonghai; Chen, Xiaowen; Chabloz, J.; Hemani, A.; Jantsch, A.; Vanmeerbeeck, G.; Kreku, Jari; Tiensyrjä, Kari; Ieromnimon, F.; Kritharidis, D.; Wiefrink, A.; Vanthournout, B.; Martin, P.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI). Los Alamitos, CA, USA : Institute of Electrical and Electronic Engineers IEEE, 2010. p. 518-523.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

TY - GEN

T1 - Mapping Optimisation for Scalable Multi-core ARchiTecture

T2 - The MOSART Approach

AU - Candaele, P.

AU - Aguirre, S.

AU - Sarlotte, M.

AU - Anagnostopoulos, I.

AU - Xydis, S.

AU - Bartzas, A.

AU - Bekiaris, D.

AU - Soudris, D.

AU - Lu, Zhonghai

AU - Chen, Xiaowen

AU - Chabloz, J.

AU - Hemani, A.

AU - Jantsch, A.

AU - Vanmeerbeeck, G.

AU - Kreku, Jari

AU - Tiensyrjä, Kari

AU - Ieromnimon, F.

AU - Kritharidis, D.

AU - Wiefrink, A.

AU - Vanthournout, B.

AU - Martin, P.

PY - 2010

Y1 - 2010

N2 - The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)

AB - The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)

U2 - 10.1109/ISVLSI.2010.71

DO - 10.1109/ISVLSI.2010.71

M3 - Conference article in proceedings

SN - 978-1-4244-7321-2

SP - 518

EP - 523

BT - Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)

PB - Institute of Electrical and Electronic Engineers IEEE

CY - Los Alamitos, CA, USA

ER -

Candaele P, Aguirre S, Sarlotte M, Anagnostopoulos I, Xydis S, Bartzas A et al. Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI). Los Alamitos, CA, USA: Institute of Electrical and Electronic Engineers IEEE. 2010. p. 518-523 https://doi.org/10.1109/ISVLSI.2010.71