Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

P. Candaele; S. Aguirre; M. Sarlotte; I. Anagnostopoulos; S. Xydis; A. Bartzas; D. Bekiaris; D. Soudris; Zhonghai Lu; Xiaowen Chen; J. Chabloz; A. Hemani; A. Jantsch; G. Vanmeerbeeck; Jari Kreku; Kari Tiensyrjä; F. Ieromnimon; D. Kritharidis; A. Wiefrink; B. Vanthournout; P. Martin

doi:10.1109/ISVLSI.2010.71

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

P. Candaele, S. Aguirre, M. Sarlotte, I. Anagnostopoulos, S. Xydis, A. Bartzas, D. Bekiaris, D. Soudris, Zhonghai Lu, Xiaowen Chen, J. Chabloz, A. Hemani, A. Jantsch, G. Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, F. Ieromnimon, D. Kritharidis, A. Wiefrink, B. VanthournoutP. Martin

VTT Technical Research Centre of Finland

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)

Original language	English
Title of host publication	Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)
Place of Publication	Los Alamitos, CA, USA
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	518-523
ISBN (Electronic)	978-1-4244-7320-5
ISBN (Print)	978-1-4244-7321-2
DOIs	https://doi.org/10.1109/ISVLSI.2010.71
Publication status	Published - 2010
MoE publication type	A4 Article in a conference publication
Event	IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI) - Lixouri, Kefalonia, Greece Duration: 5 Jul 2010 → 7 Jul 2010

Conference

Conference	IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)
Abbreviated title	VLSI 2010
Country/Territory	Greece
City	Lixouri, Kefalonia
Period	5/07/10 → 7/07/10

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10.1109/ISVLSI.2010.71

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Candaele, P., Aguirre, S., Sarlotte, M., Anagnostopoulos, I., Xydis, S., Bartzas, A., Bekiaris, D., Soudris, D., Lu, Z., Chen, X., Chabloz, J., Hemani, A., Jantsch, A., Vanmeerbeeck, G., Kreku, J., Tiensyrjä, K., Ieromnimon, F., Kritharidis, D., Wiefrink, A., ... Martin, P. (2010). Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI) (pp. 518-523). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/ISVLSI.2010.71

@inproceedings{65b103d9e26a46be8c6e805e47c87fbc,

title = "Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach",

abstract = "The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)",

author = "P. Candaele and S. Aguirre and M. Sarlotte and I. Anagnostopoulos and S. Xydis and A. Bartzas and D. Bekiaris and D. Soudris and Zhonghai Lu and Xiaowen Chen and J. Chabloz and A. Hemani and A. Jantsch and G. Vanmeerbeeck and Jari Kreku and Kari Tiensyrj{\"a} and F. Ieromnimon and D. Kritharidis and A. Wiefrink and B. Vanthournout and P. Martin",

year = "2010",

doi = "10.1109/ISVLSI.2010.71",

language = "English",

isbn = "978-1-4244-7321-2",

pages = "518--523",

booktitle = "Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI), VLSI 2010 ; Conference date: 05-07-2010 Through 07-07-2010",

}

Candaele, P, Aguirre, S, Sarlotte, M, Anagnostopoulos, I, Xydis, S, Bartzas, A, Bekiaris, D, Soudris, D, Lu, Z, Chen, X, Chabloz, J, Hemani, A, Jantsch, A, Vanmeerbeeck, G, Kreku, J, Tiensyrjä, K, Ieromnimon, F, Kritharidis, D, Wiefrink, A, Vanthournout, B & Martin, P 2010, Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. in Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI). IEEE Institute of Electrical and Electronic Engineers, Los Alamitos, CA, USA, pp. 518-523, IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI), Lixouri, Kefalonia, Greece, 5/07/10. https://doi.org/10.1109/ISVLSI.2010.71

Mapping Optimisation for Scalable Multi-core ARchiTecture : The MOSART Approach. / Candaele, P.; Aguirre, S.; Sarlotte, M. et al.

Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI). Los Alamitos, CA, USA : IEEE Institute of Electrical and Electronic Engineers, 2010. p. 518-523.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Mapping Optimisation for Scalable Multi-core ARchiTecture

T2 - IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)

AU - Candaele, P.

AU - Aguirre, S.

AU - Sarlotte, M.

AU - Anagnostopoulos, I.

AU - Xydis, S.

AU - Bartzas, A.

AU - Bekiaris, D.

AU - Soudris, D.

AU - Lu, Zhonghai

AU - Chen, Xiaowen

AU - Chabloz, J.

AU - Hemani, A.

AU - Jantsch, A.

AU - Vanmeerbeeck, G.

AU - Kreku, Jari

AU - Tiensyrjä, Kari

AU - Ieromnimon, F.

AU - Kritharidis, D.

AU - Wiefrink, A.

AU - Vanthournout, B.

AU - Martin, P.

PY - 2010

Y1 - 2010

N2 - The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)

AB - The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application. (9 refs.)

U2 - 10.1109/ISVLSI.2010.71

DO - 10.1109/ISVLSI.2010.71

M3 - Conference article in proceedings

SN - 978-1-4244-7321-2

SP - 518

EP - 523

BT - Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2010 (ISVLSI)

PB - IEEE Institute of Electrical and Electronic Engineers

CY - Los Alamitos, CA, USA

Y2 - 5 July 2010 through 7 July 2010

ER -

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

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Conference

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