Massively parallel processing on a chip - architectural challenges

BOF session on Massively Parallel Processing on a Chip

    Research output: Contribution to conferenceOther conference contributionScientific

    Abstract

    In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.
    Original languageEnglish
    Number of pages15
    Publication statusPublished - 2006
    MoE publication typeNot Eligible
    Event20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 - Rhodes, Greece
    Duration: 25 Apr 200629 Apr 2006

    Workshop

    Workshop20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06
    CountryGreece
    CityRhodes
    Period25/04/0629/04/06

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    Data storage equipment
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    Keywords

    • massively parallel computing
    • computer architecture
    • MP-SOC
    • CMP
    • multi-core

    Cite this

    Forsell, M. (2006). Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip. 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06, Rhodes, Greece.
    Forsell, Martti. / Massively parallel processing on a chip - architectural challenges : BOF session on Massively Parallel Processing on a Chip. 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06, Rhodes, Greece.15 p.
    @conference{bafeb873a6734e1794445c01b1b3671c,
    title = "Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip",
    abstract = "In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.",
    keywords = "massively parallel computing, computer architecture, MP-SOC, CMP, multi-core",
    author = "Martti Forsell",
    note = "CA2: tk703 PGN: 15; 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 ; Conference date: 25-04-2006 Through 29-04-2006",
    year = "2006",
    language = "English",

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    Forsell, M 2006, 'Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip' 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06, Rhodes, Greece, 25/04/06 - 29/04/06, .

    Massively parallel processing on a chip - architectural challenges : BOF session on Massively Parallel Processing on a Chip. / Forsell, Martti.

    2006. 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06, Rhodes, Greece.

    Research output: Contribution to conferenceOther conference contributionScientific

    TY - CONF

    T1 - Massively parallel processing on a chip - architectural challenges

    T2 - BOF session on Massively Parallel Processing on a Chip

    AU - Forsell, Martti

    N1 - CA2: tk703 PGN: 15

    PY - 2006

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    N2 - In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.

    AB - In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.

    KW - massively parallel computing

    KW - computer architecture

    KW - MP-SOC

    KW - CMP

    KW - multi-core

    M3 - Other conference contribution

    ER -

    Forsell M. Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip. 2006. 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06, Rhodes, Greece.