Abstract
In this presentation we will give a short survey of
architectural challenges related to massively parallel
processing on a chip. Topics discussed include latency of
the intercommunication network, cache cohe-rency, speed
difference between processor cores and memories,
intercommunication bandwidth, synch-ronization of
subtasks, exploitation of instruction-level parallelism,
single chip memory bottleneck, and implementation power
area and performance issues.
| Original language | English |
|---|---|
| Number of pages | 15 |
| Publication status | Published - 2006 |
| MoE publication type | Not Eligible |
| Event | 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 - Rhodes, Greece Duration: 25 Apr 2006 → 29 Apr 2006 |
Workshop
| Workshop | 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 |
|---|---|
| Country/Territory | Greece |
| City | Rhodes |
| Period | 25/04/06 → 29/04/06 |
Keywords
- massively parallel computing
- computer architecture
- MP-SOC
- CMP
- multi-core