Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip

    Research output: Contribution to conferenceOther conference contributionScientific

    Abstract

    In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.
    Original languageEnglish
    Number of pages15
    Publication statusPublished - 2006
    MoE publication typeNot Eligible
    Event20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 - Rhodes, Greece
    Duration: 25 Apr 200629 Apr 2006

    Workshop

    Workshop20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06
    CountryGreece
    CityRhodes
    Period25/04/0629/04/06

    Keywords

    • massively parallel computing
    • computer architecture
    • MP-SOC
    • CMP
    • multi-core

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  • Cite this

    Forsell, M. (2006). Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip. 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06, Rhodes, Greece.