In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.
|Number of pages||15|
|Publication status||Published - 2006|
|MoE publication type||Not Eligible|
|Event||20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 - Rhodes, Greece|
Duration: 25 Apr 2006 → 29 Apr 2006
|Workshop||20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06|
|Period||25/04/06 → 29/04/06|
- massively parallel computing
- computer architecture
Forsell, M. (2006). Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip. 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06, Rhodes, Greece.