Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip

Martti Forsell

Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip

Martti Forsell

Research output: Contribution to conference › Other conference contribution › Scientific

Abstract

In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.

Original language	English
Number of pages	15
Publication status	Published - 2006
MoE publication type	Not Eligible
Event	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 - Rhodes, Greece Duration: 25 Apr 2006 → 29 Apr 2006

Workshop

Workshop	20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06
Country/Territory	Greece
City	Rhodes
Period	25/04/06 → 29/04/06

Keywords

massively parallel computing
computer architecture
MP-SOC
CMP
multi-core

Cite this

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title = "Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip",

abstract = "In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.",

keywords = "massively parallel computing, computer architecture, MP-SOC, CMP, multi-core",

author = "Martti Forsell",

note = "CA2: tk703 PGN: 15; 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06 ; Conference date: 25-04-2006 Through 29-04-2006",

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PY - 2006

Y1 - 2006

N2 - In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.

AB - In this presentation we will give a short survey of architectural challenges related to massively parallel processing on a chip. Topics discussed include latency of the intercommunication network, cache cohe-rency, speed difference between processor cores and memories, intercommunication bandwidth, synch-ronization of subtasks, exploitation of instruction-level parallelism, single chip memory bottleneck, and implementation power area and performance issues.

KW - massively parallel computing

KW - computer architecture

KW - MP-SOC

KW - CMP

KW - multi-core

M3 - Other conference contribution

Y2 - 25 April 2006 through 29 April 2006

ER -

Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip

Abstract

Workshop

Keywords

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Cite this