Massively parallel processing on a chip - architectural challenges: BOF session on Massively Parallel Processing on a Chip

Keyphrases

• Massively Parallel Computation 100%
• Architectural Challenges 100%
• Intercommunication 66%
• Latency 33%
• Processor Core 33%
• Single chip 33%
• Instruction-level Parallelism 33%
• Performance Issues 33%
• Speed Difference 33%
• Memory Bottleneck 33%
• In-network Caching 33%

INIS

• parallel processing 100%
• performance 33%
• levels 33%
• surveys 33%
• implementation 33%
• speed 33%
• power 33%
• exploitation 33%

Computer Science

• Instruction-Level Parallelism 33%
• Performance Issue 33%
• single-chip 33%
• Processor Core 33%