Abstract
A memory unit (500) for handling data memory references of a multi-threaded processor provided with interleaved inter-thread pipeline in emulated shared memory (ESM) architectures, comprising a step cache (504) defining associative cache memory array in which data stays valid till the end of ongoing step of multithreaded execution, said memory array incorporating a plurality of cache lines with data fields, each line, preferably exclusively, containing a data field for address tag and a data field thread id of the first thread referring to a data memory location specified by the address tag, a scratchpad (506) defining a memory buffer for storing internal data of multi-operations, such as intermediate results, said buffer including, preferably exclusively, a single data field for each thread of the processor, wherein the memory unit is configured to access the step cache for a cache search and scratchpad for retrieving and/or storing said internal data at different clock cycles and different stages of the processor pipeline during multioperation execution involving data memory (508) reference by the processor. A corresponding method for handling memory references is also presented.
Patent family as of 12.10.2021
CN105393210 A 20160309 CN201480041469 20140521
CN105393210 B 20181113 CN201480041469 20140521
DE602013066391 D1 20200326 DE201360066391T 20130522
EP2806361 A1 20141126 EP20130168732 20130522
EP2806361 B1 20200304 EP20130168732 20130522
KR102254585 B1 20210524 KR20157035775 20140521
KR20160010580 A 20160127 KR20157035775 20140521
US10073782 BB 20180911 US20140892446 20140521
US2016124856 AA 20160505 US20140892446 20140521
WO14188073 A1 20141127 WO2014FI50391 20140521
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| Original language | English |
|---|---|
| Patent number | EP2806361 |
| IPC | G06F 12/ 084 A N |
| Priority date | 22/05/13 |
| Publication status | Published - 26 Nov 2014 |
| MoE publication type | H1 Granted patent |