MEMS on cavity-SOI wafers

Hannu Luoto, Kimmo Henttinen (Corresponding Author), Tommi Suni, James Dekker, Jari Mäkinen, Altti Torkkeli

    Research output: Contribution to journalArticleScientificpeer-review

    25 Citations (Scopus)

    Abstract

    Silicon-on-insulator wafers with pre-etched cavities provide freedom to MEMS design. We have studied direct bonding and mechanical thinning of pre-etched silicon wafers. We have found out that during the thinning process the flexibility of the diaphragm causes a variation in their thickness. The integrity, thickness variation and shape of thinned diaphragms are dictated by cavity dimensions, SOI thickness, cavity vacuum and thinning process. These variables have been in this study put together to form design rules for cavity-SOI manufacturing. The pre-etched cavities enable the release etching of SOI devices using dry etching. We have demonstrated fabrication and functionality of two different types of MEMS-devices.

    Original languageEnglish
    Pages (from-to)328-332
    JournalSolid-State Electronics
    Volume51
    Issue number2
    DOIs
    Publication statusPublished - 2007
    MoE publication typeA1 Journal article-refereed

    Keywords

    • Cavity-SOI
    • SOI
    • Silicon-on-insulator
    • wafer bonding
    • CSOI
    • SOI-MEMS
    • MEMS
    • RF-MEMS
    • resonators

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  • Cite this

    Luoto, H., Henttinen, K., Suni, T., Dekker, J., Mäkinen, J., & Torkkeli, A. (2007). MEMS on cavity-SOI wafers. Solid-State Electronics, 51(2), 328-332. https://doi.org/10.1016/j.sse.2007.01.007