Method for forming a cavity structure on soi substrate and cavity structure formed on soi substrate

Jyrki Kiihamaeki

Method for forming a cavity structure on soi substrate and cavity structure formed on soi substrate

Research output: Patent › Patent

Abstract

The present publication discloses a method for forming cavities in prefabricated silicon wafers comprising a first silicon layer ( 1 ), a second monocrystalline silicon layer, or a so-called structural layer ( 3 ), oriented substantially parallel with said first silicon layer ( 1 ) and an insulating layer ( 2 ) situated between said first and second layers ( 1, 3 ). According to the method, in at least one of the conducting silicon layers ( 1, 3 ) are fabricated windows ( 4 ) extending through the thickness of the layer, and cavities are etched in the insulating layer ( 2 ) by means of etchants passed to the layer via said fabricated windows ( 4 ). According to the invention, subsequent to the fabrication step of the windows ( 4 ) and prior to the etching step, a thin porous layer ( 5 ) is formed on the surface to be processed such that the etchants can be passed through said porous layer into said cavities ( 6 ) being etched and, after the cavities ( 6 ) are etched ready, at least one supplementary layer ( 7 ) is deposited in order to render to the material of said porous layer impermeable to gases

Patent family as of 26.8.2021
CN1288724 C 20061206 CN20028019431 20020927
CN1561539 A 20050105 CN20028019431 20020927
DE60245733 D1 20140102 DE20026045733 20020927
EP1433199 A1 20040630 EP20020764899 2002092
EP1433199 B1 20131106 EP20020764899 20020927
FI114755 B 20041215 FI20010001922 20011001
FI20011922 A 20030402 FI20010001922 20011001
FI20011922 A0 20011001 FI20010001922 20011001
HK1072497 A1 20050826 HK20050105143 20050621
HK1072497 A3 20050826 HK20050105143 20050621
HK1072497 B 20070518 HK20050105143 20050621
JP2005504644 T2 20050217 JP20030533331T 20020927
KR100889115 B1 20090316 KR20047004728 20020927
KR20040037218 A 20040504 KR20047004728 20020927
US6930366 BB 20050816 US20020491193 20020927
US2004248376 AA 20041209 US20040491193 20040331
WO03030234 A1 20030410 WO2002FI00772 2002092

Link to current patent family on right

Original language	English
Patent number	EP1433199
IPC	H01L 27/ 12 A I
Priority date	27/09/02
Publication status	Published - 30 Jun 2004
MoE publication type	H1 Granted patent

Cite this

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title = "Method for forming a cavity structure on soi substrate and cavity structure formed on soi substrate",

abstract = "The present publication discloses a method for forming cavities in prefabricated silicon wafers comprising a first silicon layer ( 1 ), a second monocrystalline silicon layer, or a so-called structural layer ( 3 ), oriented substantially parallel with said first silicon layer ( 1 ) and an insulating layer ( 2 ) situated between said first and second layers ( 1, 3 ). According to the method, in at least one of the conducting silicon layers ( 1, 3 ) are fabricated windows ( 4 ) extending through the thickness of the layer, and cavities are etched in the insulating layer ( 2 ) by means of etchants passed to the layer via said fabricated windows ( 4 ). According to the invention, subsequent to the fabrication step of the windows ( 4 ) and prior to the etching step, a thin porous layer ( 5 ) is formed on the surface to be processed such that the etchants can be passed through said porous layer into said cavities ( 6 ) being etched and, after the cavities ( 6 ) are etched ready, at least one supplementary layer ( 7 ) is deposited in order to render to the material of said porous layer impermeable to gasesPatent family as of 26.8.2021 CN1288724 C 20061206 CN20028019431 20020927 CN1561539 A 20050105 CN20028019431 20020927 DE60245733 D1 20140102 DE20026045733 20020927 EP1433199 A1 20040630 EP20020764899 2002092 EP1433199 B1 20131106 EP20020764899 20020927 FI114755 B 20041215 FI20010001922 20011001 FI20011922 A 20030402 FI20010001922 20011001 FI20011922 A0 20011001 FI20010001922 20011001 HK1072497 A1 20050826 HK20050105143 20050621 HK1072497 A3 20050826 HK20050105143 20050621 HK1072497 B 20070518 HK20050105143 20050621 JP2005504644 T2 20050217 JP20030533331T 20020927 KR100889115 B1 20090316 KR20047004728 20020927 KR20040037218 A 20040504 KR20047004728 20020927 US6930366 BB 20050816 US20020491193 20020927 US2004248376 AA 20041209 US20040491193 20040331 WO03030234 A1 20030410 WO2002FI00772 2002092Link to current patent family on right ",

author = "Jyrki Kiihamaeki",

year = "2004",

month = jun,

day = "30",

language = "English",

type = "Patent",

note = "EP1433199; H01L 27/ 12 A I",

}

TY - PAT

T1 - Method for forming a cavity structure on soi substrate and cavity structure formed on soi substrate

AU - Kiihamaeki, Jyrki

PY - 2004/6/30

Y1 - 2004/6/30

N2 - The present publication discloses a method for forming cavities in prefabricated silicon wafers comprising a first silicon layer ( 1 ), a second monocrystalline silicon layer, or a so-called structural layer ( 3 ), oriented substantially parallel with said first silicon layer ( 1 ) and an insulating layer ( 2 ) situated between said first and second layers ( 1, 3 ). According to the method, in at least one of the conducting silicon layers ( 1, 3 ) are fabricated windows ( 4 ) extending through the thickness of the layer, and cavities are etched in the insulating layer ( 2 ) by means of etchants passed to the layer via said fabricated windows ( 4 ). According to the invention, subsequent to the fabrication step of the windows ( 4 ) and prior to the etching step, a thin porous layer ( 5 ) is formed on the surface to be processed such that the etchants can be passed through said porous layer into said cavities ( 6 ) being etched and, after the cavities ( 6 ) are etched ready, at least one supplementary layer ( 7 ) is deposited in order to render to the material of said porous layer impermeable to gasesPatent family as of 26.8.2021 CN1288724 C 20061206 CN20028019431 20020927 CN1561539 A 20050105 CN20028019431 20020927 DE60245733 D1 20140102 DE20026045733 20020927 EP1433199 A1 20040630 EP20020764899 2002092 EP1433199 B1 20131106 EP20020764899 20020927 FI114755 B 20041215 FI20010001922 20011001 FI20011922 A 20030402 FI20010001922 20011001 FI20011922 A0 20011001 FI20010001922 20011001 HK1072497 A1 20050826 HK20050105143 20050621 HK1072497 A3 20050826 HK20050105143 20050621 HK1072497 B 20070518 HK20050105143 20050621 JP2005504644 T2 20050217 JP20030533331T 20020927 KR100889115 B1 20090316 KR20047004728 20020927 KR20040037218 A 20040504 KR20047004728 20020927 US6930366 BB 20050816 US20020491193 20020927 US2004248376 AA 20041209 US20040491193 20040331 WO03030234 A1 20030410 WO2002FI00772 2002092Link to current patent family on right

AB - The present publication discloses a method for forming cavities in prefabricated silicon wafers comprising a first silicon layer ( 1 ), a second monocrystalline silicon layer, or a so-called structural layer ( 3 ), oriented substantially parallel with said first silicon layer ( 1 ) and an insulating layer ( 2 ) situated between said first and second layers ( 1, 3 ). According to the method, in at least one of the conducting silicon layers ( 1, 3 ) are fabricated windows ( 4 ) extending through the thickness of the layer, and cavities are etched in the insulating layer ( 2 ) by means of etchants passed to the layer via said fabricated windows ( 4 ). According to the invention, subsequent to the fabrication step of the windows ( 4 ) and prior to the etching step, a thin porous layer ( 5 ) is formed on the surface to be processed such that the etchants can be passed through said porous layer into said cavities ( 6 ) being etched and, after the cavities ( 6 ) are etched ready, at least one supplementary layer ( 7 ) is deposited in order to render to the material of said porous layer impermeable to gasesPatent family as of 26.8.2021 CN1288724 C 20061206 CN20028019431 20020927 CN1561539 A 20050105 CN20028019431 20020927 DE60245733 D1 20140102 DE20026045733 20020927 EP1433199 A1 20040630 EP20020764899 2002092 EP1433199 B1 20131106 EP20020764899 20020927 FI114755 B 20041215 FI20010001922 20011001 FI20011922 A 20030402 FI20010001922 20011001 FI20011922 A0 20011001 FI20010001922 20011001 HK1072497 A1 20050826 HK20050105143 20050621 HK1072497 A3 20050826 HK20050105143 20050621 HK1072497 B 20070518 HK20050105143 20050621 JP2005504644 T2 20050217 JP20030533331T 20020927 KR100889115 B1 20090316 KR20047004728 20020927 KR20040037218 A 20040504 KR20047004728 20020927 US6930366 BB 20050816 US20020491193 20020927 US2004248376 AA 20041209 US20040491193 20040331 WO03030234 A1 20030410 WO2002FI00772 2002092Link to current patent family on right

UR - https://worldwide.espacenet.com/patent/search/family/008561984/publication/EP1433199A1?q=EP1433199

M3 - Patent

M1 - EP1433199

ER -

Method for forming a cavity structure on soi substrate and cavity structure formed on soi substrate

Abstract

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