Millimeter-wave integrated circuits in 65-nm CMOS

M. Varonen, M. Kärkkäinen, Mikko Kantanen, K.A.I. Halonen

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    Abstract

    We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at +6-dBm power level using a 1.2 V supply with a compact chip area of 0.286 mm2. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of +7 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and +5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with -19 dBm of 1-dB output compression point.
    Original languageEnglish
    Pages (from-to)1991-2002
    Number of pages12
    JournalIEEE Journal of Solid-State Circuits
    Volume43
    Issue number9
    DOIs
    Publication statusPublished - 2008
    MoE publication typeA1 Journal article-refereed

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