MMIC Design for Radiometer Receiver at 240 GHz in 0.13 μm SiGe BiCMOS Technology

This paper introduces an MMIC radiometer receiver designed for integration into a 240 GHz radiometer receiver system using a 130-nm SiGe BiCMOS technology. The detector features an on-chip dipole antenna, an SPDT switch, a Low Noise Amplifier (LNA), a mixer, an IF amplifier, and a power detector. The resonator switch exhibits a measured minimum insertion loss of 4.2 dB, maximum isolation of 29 dB, and minimum input and output reflection coefficients of 16 dB and 20 dB, respectively. The LNA utilizes a 5 -stage cascode design, achieving a simulated gain of 28 dB at 240 GHz. The mixer, designed as a single-balanced second harmonic mixer, provides a simulated conversion gain of 0 dB. The IF amplifier, a 3 -stage differential cascode amplifier, can provide a simulated gain of 45 dB at its IF frequency. The power detector is designed using the Meyer topology for a high dynamic range contributing to the chip's ability to enhance radiometer resolution. Additionally, this paper also presents a free-space measurement conducted to verify the radiometer receiver's functionality. In the measurement, with a LO frequency set at 112 GHz, the detector provides an output voltage of 650 mV in response to an IF current of 43 mA, demonstrating its effective performance.