Abstract
The objective of this thesis work was to construct a VHDL simulation
model of a Transport Triggered processor. It was used for becoming
familiar with the Transport Triggered Architectures in order to
understand which applications it would be useful in and to see how it
would meet the requirements set for processor cores used in Systems On
Chip. The processor model consists of two global busses and seven
functional units that provide the support for data storage and
transportation, instruction fetch, conditional execution and immediate
issuing. On this platform, another five functional units were added to
enable running test algorithms on the processor. These functional units
perform operations such as addition and subtraction,
multiply-and-accumulate, shifting of a data vector, and logical
operations.
Two test algorithms were chosen to be run with the processor; 16-tap
FIR and 16-point radix-2 FFT. With these simulations the processor model
was found to be functioning properly and it could be seen that the FIR
took 16 clock cycles to run and the FFT needed 1440 cycles.
During construction of the model, the effort to design, modify and
scale a TTA processor was evaluated. It was found that adding and
removing the functional units was easy after the platform had been
designed since all the units have identical connections to the busses.
Changing the functionality of the units was also found to be simple,
since most of the functional units differ from each other by only 10-20
lines of VHDL. Therefore the TTAs would seem an attractive choice for
systems needing simple scalability and modifiability such as Systems on
Chip.
Original language | English |
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Qualification | Master Degree |
Awarding Institution |
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Place of Publication | Oulu |
Publisher | |
Publication status | Published - 2002 |
MoE publication type | G2 Master's thesis, polytechnic Master's thesis |
Keywords
- TTA
- VHDL
- DSP algorithms
- Orthogonal Frequency Division Multiplexing
- OFDM