Abstract
Moving threads is a new kind of approach for mapping the computation of
an application to multiprocessor system on chip (MP-SOC) architecture. Instead
of moving data read and write requests, extremely lightweight threads are
moved between the processor cores. As a consequence, all kinds of cache
coherence problems and need for read reply messages are eliminated. Lamport's
sequential consistency of shared memory multiprocessor systems is achieved for
free. Flexible and efficient handling of varying number of threads is
included in the architecture. In this paper we propose a processor
architecture (MTPA) for the moving threads paradigm. We describe the overall
structure, operation, instruction set, and thread management mechanism as well
as evaluate the proposed architecture with different functional unit settings
with simulations and give early silicon area and power consumption estimates.
Original language | English |
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Title of host publication | Proceedings of the 2009 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2009 |
Editors | Hamid R. Arabnia |
Pages | 198-204 |
Volume | 1 |
ISBN (Electronic) | 1-60132-122-8 |
Publication status | Published - 2009 |
MoE publication type | A4 Article in a conference publication |
Event | 2009 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2009 - Las Vegas, United States Duration: 13 Jul 2009 → 16 Jul 2009 |
Conference
Conference | 2009 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2009 |
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Abbreviated title | PDPTA 2009 |
Country/Territory | United States |
City | Las Vegas |
Period | 13/07/09 → 16/07/09 |
Keywords
- Moving threads
- parallel computing
- MP-SOC
- processor architecture
- computer architecture