Abstract
An integrated receiver consisting of RF front ends,
analog baseband chain with an analog to digital converter
(ADC) for a Synthetic Aperture Radar (SAR) implemented in
130 nm CMOS technology is presented in this paper. The
circuits are integrated on a single chip with a size of
10.88 mm2. The RF front end consists of three parallel
signal channels intended for L,C and X-band of the SAR
receiver. The baseband (BB) is selectable between 50 MHz
and 160 MHz bandwidths through switches. The ADC has
selectable mode of 5, 6, 7 and 8 bits via control
switches. The receiver has a nominal gain of 40 dB and 37
dB and noise figure of 11 dB and 13.5 dB for 160 MHz BB
filter at room temperature for L-band and C-band,
respectively. The circuits, which use a 1.2 V supply
voltage, dissipate maximum power of 650 mW with 50 MHz
baseband and 8 bit mode ADC, and maximum power of 800 mW
with 160 MHz baseband and 8 bit mode ADC.
Original language | English |
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Title of host publication | Proceedings |
Subtitle of host publication | 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 |
Publisher | IEEE Institute of Electrical and Electronic Engineers |
Pages | 713-716 |
ISBN (Electronic) | 978-1-4673-1259-2 |
ISBN (Print) | 978-1-4673-1261-5 |
DOIs | |
Publication status | Published - 2012 |
MoE publication type | Not Eligible |
Event | 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 - Seville, Spain Duration: 9 Dec 2012 → 12 Dec 2012 |
Conference
Conference | 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 |
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Abbreviated title | ICECS 2012 |
Country/Territory | Spain |
City | Seville |
Period | 9/12/12 → 12/12/12 |