Multicast-enabling Optical Switch design employing Si Buffering and Routing Elements

M. Moralis-Pegios; N. Terzenidis; G. Mourgias-Alexandris; Matteo Cherchi; Mikko Harjanne; Timo Aalto; A. Miliou; K. Vyrsokinos; N. Pleros

doi:10.1109/LPT.2018.2813012

Multicast-enabling Optical Switch design employing Si Buffering and Routing Elements

M. Moralis-Pegios, N. Terzenidis, G. Mourgias-Alexandris, Matteo Cherchi, Mikko Harjanne, Timo Aalto, A. Miliou, K. Vyrsokinos, N. Pleros

Research output: Contribution to journal › Article › Scientific › peer-review

19 Citations (Scopus)

Abstract

We demonstrate experimentally an optical switch architecture that employs μm-SOI-based circuitry for both buffering and routing purposes and operates with 10 Gb/s optical packets in both uni- and multi-cast switching forwarding modes. It comprises a hybrid Broadcast-and-Select (BS) / wavelength-routed architecture, with the BS layout being responsible for identifying the desired cluster of outgoing ports, while the wavelength-routed switch part forwards then the data to the specific outgoing port. Contention resolution at the BS switch part is offered through an μm-SOI integrated optical delay line bank and wavelength-routing is realized by means of a μm-SOI 3×3 Echelle grating router, while SOA-MZIs are employed for wavelength conversion purposes. The switch architecture has been experimentally validated with 10 Gb/s optical data packets for both uni- and multicasting operation, revealing error-free performance with <5 dB power penalty.

Original language	English
Pages (from-to)	712-715
Number of pages	4
Journal	IEEE Photonics Technology Letters
Volume	30
Issue number	8
DOIs	https://doi.org/10.1109/LPT.2018.2813012
Publication status	Published - 15 Apr 2018
MoE publication type	A1 Journal article-refereed

Keywords

Adaptive optics
Delay lines
Echelle Grating Router
Field programmable gate arrays
Integrated delay lines
Optical buffering
Optical switches
Optical waveguides
Optical wavelength conversion
Photonic integrated circuits
Silicon photonics
OtaNano

Access to Document

10.1109/LPT.2018.2813012

Cite this

@article{573ff3a281a84f5ebe701f8dcec436fa,

title = "Multicast-enabling Optical Switch design employing Si Buffering and Routing Elements",

abstract = "We demonstrate experimentally an optical switch architecture that employs μm-SOI-based circuitry for both buffering and routing purposes and operates with 10 Gb/s optical packets in both uni- and multi-cast switching forwarding modes. It comprises a hybrid Broadcast-and-Select (BS) / wavelength-routed architecture, with the BS layout being responsible for identifying the desired cluster of outgoing ports, while the wavelength-routed switch part forwards then the data to the specific outgoing port. Contention resolution at the BS switch part is offered through an μm-SOI integrated optical delay line bank and wavelength-routing is realized by means of a μm-SOI 3×3 Echelle grating router, while SOA-MZIs are employed for wavelength conversion purposes. The switch architecture has been experimentally validated with 10 Gb/s optical data packets for both uni- and multicasting operation, revealing error-free performance with <5 dB power penalty.",

keywords = "Adaptive optics, Delay lines, Echelle Grating Router, Field programmable gate arrays, Integrated delay lines, Optical buffering, Optical switches, Optical waveguides, Optical wavelength conversion, Photonic integrated circuits, Silicon photonics, OtaNano",

author = "M. Moralis-Pegios and N. Terzenidis and G. Mourgias-Alexandris and Matteo Cherchi and Mikko Harjanne and Timo Aalto and A. Miliou and K. Vyrsokinos and N. Pleros",

year = "2018",

month = apr,

day = "15",

doi = "10.1109/LPT.2018.2813012",

language = "English",

volume = "30",

pages = "712--715",

journal = "IEEE Photonics Technology Letters",

issn = "1041-1135",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

number = "8",

}

TY - JOUR

T1 - Multicast-enabling Optical Switch design employing Si Buffering and Routing Elements

AU - Moralis-Pegios, M.

AU - Terzenidis, N.

AU - Mourgias-Alexandris, G.

AU - Cherchi, Matteo

AU - Harjanne, Mikko

AU - Aalto, Timo

AU - Miliou, A.

AU - Vyrsokinos, K.

AU - Pleros, N.

PY - 2018/4/15

Y1 - 2018/4/15

N2 - We demonstrate experimentally an optical switch architecture that employs μm-SOI-based circuitry for both buffering and routing purposes and operates with 10 Gb/s optical packets in both uni- and multi-cast switching forwarding modes. It comprises a hybrid Broadcast-and-Select (BS) / wavelength-routed architecture, with the BS layout being responsible for identifying the desired cluster of outgoing ports, while the wavelength-routed switch part forwards then the data to the specific outgoing port. Contention resolution at the BS switch part is offered through an μm-SOI integrated optical delay line bank and wavelength-routing is realized by means of a μm-SOI 3×3 Echelle grating router, while SOA-MZIs are employed for wavelength conversion purposes. The switch architecture has been experimentally validated with 10 Gb/s optical data packets for both uni- and multicasting operation, revealing error-free performance with <5 dB power penalty.

AB - We demonstrate experimentally an optical switch architecture that employs μm-SOI-based circuitry for both buffering and routing purposes and operates with 10 Gb/s optical packets in both uni- and multi-cast switching forwarding modes. It comprises a hybrid Broadcast-and-Select (BS) / wavelength-routed architecture, with the BS layout being responsible for identifying the desired cluster of outgoing ports, while the wavelength-routed switch part forwards then the data to the specific outgoing port. Contention resolution at the BS switch part is offered through an μm-SOI integrated optical delay line bank and wavelength-routing is realized by means of a μm-SOI 3×3 Echelle grating router, while SOA-MZIs are employed for wavelength conversion purposes. The switch architecture has been experimentally validated with 10 Gb/s optical data packets for both uni- and multicasting operation, revealing error-free performance with <5 dB power penalty.

KW - Adaptive optics

KW - Delay lines

KW - Echelle Grating Router

KW - Field programmable gate arrays

KW - Integrated delay lines

KW - Optical buffering

KW - Optical switches

KW - Optical waveguides

KW - Optical wavelength conversion

KW - Photonic integrated circuits

KW - Silicon photonics

KW - OtaNano

UR - http://www.scopus.com/inward/record.url?scp=85043355632&partnerID=8YFLogxK

U2 - 10.1109/LPT.2018.2813012

DO - 10.1109/LPT.2018.2813012

M3 - Article

AN - SCOPUS:85043355632

VL - 30

SP - 712

EP - 715

JO - IEEE Photonics Technology Letters

JF - IEEE Photonics Technology Letters

SN - 1041-1135

IS - 8

ER -

Multicast-enabling Optical Switch design employing Si Buffering and Routing Elements

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

OtaNano

Cite this

Multicast-enabling Optical Switch design employing Si Buffering and Routing Elements

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Equipment

OtaNano

Cite this