Novel interpolator structure for digital symbol synchronisation

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    4 Citations (Scopus)

    Abstract

    Timing adjustment in a digital modem is performed by interpolation after sampling with a fixed clock. A novel interpolator structure is proposed to avoid extrapolation problem, which arises if the fixed clock sampling rate is assumed to be equal to the nominal sampling rate of the interpolator output signal. The simulations indicate that the proposed structure works well and is superior to the conventional implementation.
    Original languageEnglish
    Title of host publicationIEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics, 2005
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages1014 - 1017
    ISBN (Print)0-7803-9068-7
    DOIs
    Publication statusPublished - 15 Aug 2005
    MoE publication typeA4 Article in a conference publication
    Event2005 IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics - Honolulu, United States
    Duration: 3 Apr 20057 Apr 2005

    Conference

    Conference2005 IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics
    CountryUnited States
    CityHonolulu
    Period3/04/057/04/05

    Fingerprint

    Synchronization
    Sampling
    Clocks
    Modems
    Extrapolation
    Interpolation

    Keywords

    • digital symbol synchronisation
    • timing
    • timing adjustment
    • sampling rate
    • synchronisation
    • signal sampling
    • interpolation
    • filtering theory
    • digital filters

    Cite this

    Kiviranta, M. (2005). Novel interpolator structure for digital symbol synchronisation. In IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics, 2005 (pp. 1014 - 1017). IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/WCACEM.2005.1469755
    Kiviranta, Markku. / Novel interpolator structure for digital symbol synchronisation. IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics, 2005. IEEE Institute of Electrical and Electronic Engineers , 2005. pp. 1014 - 1017
    @inproceedings{d0cf3a8f9b9a495ab7c850c6bea712f5,
    title = "Novel interpolator structure for digital symbol synchronisation",
    abstract = "Timing adjustment in a digital modem is performed by interpolation after sampling with a fixed clock. A novel interpolator structure is proposed to avoid extrapolation problem, which arises if the fixed clock sampling rate is assumed to be equal to the nominal sampling rate of the interpolator output signal. The simulations indicate that the proposed structure works well and is superior to the conventional implementation.",
    keywords = "digital symbol synchronisation, timing, timing adjustment, sampling rate, synchronisation, signal sampling, interpolation, filtering theory, digital filters",
    author = "Markku Kiviranta",
    year = "2005",
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    Kiviranta, M 2005, Novel interpolator structure for digital symbol synchronisation. in IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics, 2005. IEEE Institute of Electrical and Electronic Engineers , pp. 1014 - 1017, 2005 IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics, Honolulu, United States, 3/04/05. https://doi.org/10.1109/WCACEM.2005.1469755

    Novel interpolator structure for digital symbol synchronisation. / Kiviranta, Markku.

    IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics, 2005. IEEE Institute of Electrical and Electronic Engineers , 2005. p. 1014 - 1017.

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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    Kiviranta M. Novel interpolator structure for digital symbol synchronisation. In IEEE/ACES International Conference on Wireless Communications and Applied Computational Electromagnetics, 2005. IEEE Institute of Electrical and Electronic Engineers . 2005. p. 1014 - 1017 https://doi.org/10.1109/WCACEM.2005.1469755