On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

M. Moralis-Pegios, G. Mourgias-Alexandris, N. Terzenidis, M. Cherchi, M. Harjanne, T. Aalto, A. Miliou, N. Pleros, K. Vyrsokinos

Research output: Contribution to journalArticleScientificpeer-review

9 Citations (Scopus)

Abstract

We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.

Original languageEnglish
Pages (from-to)31-34
Number of pages4
JournalIEEE Photonics Technology Letters
Volume30
Issue number1
DOIs
Publication statusPublished - 2018
MoE publication typeA1 Journal article-refereed

Fingerprint

Electric delay lines
Silicon
delay lines
slots
Buffers
Waveguides
buffers
chips
insulators
silicon
Service oriented architecture (SOA)
Wavelength
waveguides
converters
wavelengths

Keywords

  • integrated delay lines
  • Optical buffering
  • Photonic integrated circuits
  • Silicon photonics
  • Time-Slot Interchanger

Cite this

Moralis-Pegios, M. ; Mourgias-Alexandris, G. ; Terzenidis, N. ; Cherchi, M. ; Harjanne, M. ; Aalto, T. ; Miliou, A. ; Pleros, N. ; Vyrsokinos, K. / On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers. In: IEEE Photonics Technology Letters. 2018 ; Vol. 30, No. 1. pp. 31-34.
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abstract = "We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.",
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Moralis-Pegios, M, Mourgias-Alexandris, G, Terzenidis, N, Cherchi, M, Harjanne, M, Aalto, T, Miliou, A, Pleros, N & Vyrsokinos, K 2018, 'On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers', IEEE Photonics Technology Letters, vol. 30, no. 1, pp. 31-34. https://doi.org/10.1109/LPT.2017.2773146

On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers. / Moralis-Pegios, M.; Mourgias-Alexandris, G.; Terzenidis, N.; Cherchi, M.; Harjanne, M.; Aalto, T.; Miliou, A.; Pleros, N.; Vyrsokinos, K.

In: IEEE Photonics Technology Letters, Vol. 30, No. 1, 2018, p. 31-34.

Research output: Contribution to journalArticleScientificpeer-review

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AU - Moralis-Pegios, M.

AU - Mourgias-Alexandris, G.

AU - Terzenidis, N.

AU - Cherchi, M.

AU - Harjanne, M.

AU - Aalto, T.

AU - Miliou, A.

AU - Pleros, N.

AU - Vyrsokinos, K.

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AB - We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.

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