On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

Miltiadis Moralis-Pegios, George Mourgias-Alexandris, Nikos Terzenidis, Matteo Cherchi, Mikko Harjanne, Timo Aalto, Amalia Miliou, N. Pleros, Konstantinos Vyrsokinos

    Research output: Contribution to journalArticleScientificpeer-review

    10 Citations (Scopus)

    Abstract

    We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.

    Original languageEnglish
    Pages (from-to)31-34
    JournalIEEE Photonics Technology Letters
    Volume30
    Issue number1
    DOIs
    Publication statusPublished - 2018
    MoE publication typeA1 Journal article-refereed

    Fingerprint

    Electric delay lines
    Silicon
    delay lines
    slots
    Buffers
    Waveguides
    buffers
    chips
    insulators
    silicon
    Service oriented architecture (SOA)
    Wavelength
    waveguides
    converters
    wavelengths

    Keywords

    • integrated delay lines
    • Optical buffering
    • Photonic integrated circuits
    • Silicon photonics
    • Time-Slot Interchanger

    Cite this

    Moralis-Pegios, Miltiadis ; Mourgias-Alexandris, George ; Terzenidis, Nikos ; Cherchi, Matteo ; Harjanne, Mikko ; Aalto, Timo ; Miliou, Amalia ; Pleros, N. ; Vyrsokinos, Konstantinos. / On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers. In: IEEE Photonics Technology Letters. 2018 ; Vol. 30, No. 1. pp. 31-34.
    @article{8310eb2e44c24b57baa8c2fdf6a92270,
    title = "On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers",
    abstract = "We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.",
    keywords = "integrated delay lines, Optical buffering, Photonic integrated circuits, Silicon photonics, Time-Slot Interchanger",
    author = "Miltiadis Moralis-Pegios and George Mourgias-Alexandris and Nikos Terzenidis and Matteo Cherchi and Mikko Harjanne and Timo Aalto and Amalia Miliou and N. Pleros and Konstantinos Vyrsokinos",
    year = "2018",
    doi = "10.1109/LPT.2017.2773146",
    language = "English",
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    Moralis-Pegios, M, Mourgias-Alexandris, G, Terzenidis, N, Cherchi, M, Harjanne, M, Aalto, T, Miliou, A, Pleros, N & Vyrsokinos, K 2018, 'On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers', IEEE Photonics Technology Letters, vol. 30, no. 1, pp. 31-34. https://doi.org/10.1109/LPT.2017.2773146

    On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers. / Moralis-Pegios, Miltiadis; Mourgias-Alexandris, George; Terzenidis, Nikos; Cherchi, Matteo; Harjanne, Mikko; Aalto, Timo; Miliou, Amalia; Pleros, N.; Vyrsokinos, Konstantinos.

    In: IEEE Photonics Technology Letters, Vol. 30, No. 1, 2018, p. 31-34.

    Research output: Contribution to journalArticleScientificpeer-review

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    T1 - On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

    AU - Moralis-Pegios, Miltiadis

    AU - Mourgias-Alexandris, George

    AU - Terzenidis, Nikos

    AU - Cherchi, Matteo

    AU - Harjanne, Mikko

    AU - Aalto, Timo

    AU - Miliou, Amalia

    AU - Pleros, N.

    AU - Vyrsokinos, Konstantinos

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    AB - We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.

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    KW - Optical buffering

    KW - Photonic integrated circuits

    KW - Silicon photonics

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