On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

Miltiadis Moralis-Pegios, George Mourgias-Alexandris, Nikos Terzenidis, Matteo Cherchi, Mikko Harjanne, Timo Aalto, Amalia Miliou, N. Pleros, Konstantinos Vyrsokinos

    Research output: Contribution to journalArticleScientificpeer-review

    28 Citations (Scopus)


    We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm² on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.
    Original languageEnglish
    Pages (from-to)31-34
    JournalIEEE Photonics Technology Letters
    Issue number1
    Publication statusPublished - 2018
    MoE publication typeA1 Journal article-refereed


    This work was supported in part by the EC through H2020 Projects ICT-STREAMS under Contract 688172 and in part by L3MATRIX under Contract 688544.


    • integrated delay lines
    • Optical buffering
    • Photonic integrated circuits
    • Silicon photonics
    • Time-Slot Interchanger
    • OtaNano


    Dive into the research topics of 'On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers'. Together they form a unique fingerprint.

    Cite this