On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

Miltiadis Moralis-Pegios; George Mourgias-Alexandris; Nikos Terzenidis; Matteo Cherchi; Mikko Harjanne; Timo Aalto; Amalia Miliou; N. Pleros; Konstantinos Vyrsokinos

doi:10.1109/LPT.2017.2773146

On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

Miltiadis Moralis-Pegios
, George Mourgias-Alexandris
, Nikos Terzenidis
, Matteo Cherchi
, Mikko Harjanne
, Timo Aalto
, Amalia Miliou
, N. Pleros
, Konstantinos Vyrsokinos

Aristotle University of Thessaloniki

Research output: Contribution to journal › Article › Scientific › peer-review

30 Citations (Scopus)

Abstract

We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm² on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.

Original language	English
Pages (from-to)	31-34
Journal	IEEE Photonics Technology Letters
Volume	30
Issue number	1
DOIs	https://doi.org/10.1109/LPT.2017.2773146
Publication status	Published - 2018
MoE publication type	A1 Journal article-refereed

Funding

This work was supported in part by the EC through H2020 Projects ICT-STREAMS under Contract 688172 and in part by L3MATRIX under Contract 688544.

Keywords

integrated delay lines
Optical buffering
Photonic integrated circuits
Silicon photonics
Time-Slot Interchanger
OtaNano

Access to Document

10.1109/LPT.2017.2773146

Cite this

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title = "On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers",

abstract = "We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm² on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.",

keywords = "integrated delay lines, Optical buffering, Photonic integrated circuits, Silicon photonics, Time-Slot Interchanger, OtaNano",

author = "Miltiadis Moralis-Pegios and George Mourgias-Alexandris and Nikos Terzenidis and Matteo Cherchi and Mikko Harjanne and Timo Aalto and Amalia Miliou and N. Pleros and Konstantinos Vyrsokinos",

year = "2018",

doi = "10.1109/LPT.2017.2773146",

language = "English",

volume = "30",

pages = "31--34",

journal = "IEEE Photonics Technology Letters",

issn = "1041-1135",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

number = "1",

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T1 - On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

AU - Moralis-Pegios, Miltiadis

AU - Mourgias-Alexandris, George

AU - Terzenidis, Nikos

AU - Cherchi, Matteo

AU - Harjanne, Mikko

AU - Aalto, Timo

AU - Miliou, Amalia

AU - Pleros, N.

AU - Vyrsokinos, Konstantinos

PY - 2018

Y1 - 2018

N2 - We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm² on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.

AB - We demonstrate integrated Silicon-on-Insulator (SOI) spiral waveguides with record-high 2.6ns/mm² on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and Time-Slot Interchanger (TSI) applications with 10Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different length, providing variable delays of 6.5nsec, 11.3nsec and 17.2nsec, respectively. Utilizing two SOA-MZI wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5nsec up to 17.2nsec and successful timeslot interchanging for 10Gb/s optical packets are presented.

KW - integrated delay lines

KW - Optical buffering

KW - Photonic integrated circuits

KW - Silicon photonics

KW - Time-Slot Interchanger

KW - OtaNano

UR - https://www.scopus.com/pages/publications/85034224156

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DO - 10.1109/LPT.2017.2773146

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EP - 34

JO - IEEE Photonics Technology Letters

JF - IEEE Photonics Technology Letters

IS - 1

ER -

On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

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On-chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers

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