On the performance and cost of some PRAM models on CMP hardware

Martti Forsell (Corresponding Author)

    Research output: Contribution to journalArticleScientificpeer-review

    5 Citations (Scopus)


    The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-efficient implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest simulation cost and highest performance/area and performance/power figures.
    Original languageEnglish
    Pages (from-to)387-404
    Number of pages18
    JournalInternational Journal of Foundations of Computer Science
    Issue number3
    Publication statusPublished - 2010
    MoE publication typeA1 Journal article-refereed


    • Parallel computing
    • Performance
    • Power consumption
    • PRAM
    • Silicon area


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