On the performance and cost of some PRAM models on CMP hardware

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

3 Citations (Scopus)

Abstract

The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-effective implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest relative cost and highest performance/area and performance/power figures. (15 refs.)
Original languageEnglish
Title of host publicationProceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008
Place of PublicationPiscataway, NJ, USA
PublisherIEEE Institute of Electrical and Electronic Engineers
Pages178-185
ISBN (Print)978-1-4244-1693-6, 978-1-4244-1694-3
DOIs
Publication statusPublished - 2008
MoE publication typeA4 Article in a conference publication
EventIEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008 - Miami, FL, United States
Duration: 14 Apr 200818 Apr 2008

Conference

ConferenceIEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008
Abbreviated titleIPDPS 2008
CountryUnited States
CityMiami, FL
Period14/04/0818/04/08

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Hardware
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Parallel processing systems

Cite this

Forsell, M. (2008). On the performance and cost of some PRAM models on CMP hardware. In Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008 (pp. 178-185). Piscataway, NJ, USA: IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/IPDPS.2008.4536126
Forsell, Martti. / On the performance and cost of some PRAM models on CMP hardware. Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008 . Piscataway, NJ, USA : IEEE Institute of Electrical and Electronic Engineers , 2008. pp. 178-185
@inproceedings{b8069588855c44409baa12c2fd898cf4,
title = "On the performance and cost of some PRAM models on CMP hardware",
abstract = "The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-effective implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest relative cost and highest performance/area and performance/power figures. (15 refs.)",
author = "Martti Forsell",
year = "2008",
doi = "10.1109/IPDPS.2008.4536126",
language = "English",
isbn = "978-1-4244-1693-6",
pages = "178--185",
booktitle = "Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008",
publisher = "IEEE Institute of Electrical and Electronic Engineers",
address = "United States",

}

Forsell, M 2008, On the performance and cost of some PRAM models on CMP hardware. in Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008 . IEEE Institute of Electrical and Electronic Engineers , Piscataway, NJ, USA, pp. 178-185, IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, FL, United States, 14/04/08. https://doi.org/10.1109/IPDPS.2008.4536126

On the performance and cost of some PRAM models on CMP hardware. / Forsell, Martti.

Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008 . Piscataway, NJ, USA : IEEE Institute of Electrical and Electronic Engineers , 2008. p. 178-185.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

TY - GEN

T1 - On the performance and cost of some PRAM models on CMP hardware

AU - Forsell, Martti

PY - 2008

Y1 - 2008

N2 - The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-effective implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest relative cost and highest performance/area and performance/power figures. (15 refs.)

AB - The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-effective implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest relative cost and highest performance/area and performance/power figures. (15 refs.)

U2 - 10.1109/IPDPS.2008.4536126

DO - 10.1109/IPDPS.2008.4536126

M3 - Conference article in proceedings

SN - 978-1-4244-1693-6

SN - 978-1-4244-1694-3

SP - 178

EP - 185

BT - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008

PB - IEEE Institute of Electrical and Electronic Engineers

CY - Piscataway, NJ, USA

ER -

Forsell M. On the performance and cost of some PRAM models on CMP hardware. In Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2008 . Piscataway, NJ, USA: IEEE Institute of Electrical and Electronic Engineers . 2008. p. 178-185 https://doi.org/10.1109/IPDPS.2008.4536126