On the performance and cost of some PRAM models on CMP hardware

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    Abstract

    The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-effective implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest relative cost and highest performance/area and performance/power figures.
    Original languageEnglish
    Title of host publicationProceedings
    Subtitle of host publicationIEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008
    Place of PublicationUSA
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Number of pages8
    ISBN (Print)978-1-4244-1693-6, 978-1-4244-1694-3
    DOIs
    Publication statusPublished - 2008
    MoE publication typeA4 Article in a conference publication
    EventIEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008 - Miami, FL, United States
    Duration: 14 Apr 200818 Apr 2008

    Conference

    ConferenceIEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008
    Abbreviated titleIPDPS 2008
    CountryUnited States
    CityMiami, FL
    Period14/04/0818/04/08

    Fingerprint

    Hardware
    Costs
    Parallel processing systems

    Keywords

    • parallel computing
    • performance modeling
    • silicon area modeling
    • power consumption modeling
    • PRAM
    • CMP

    Cite this

    Forsell, M. (2008). On the performance and cost of some PRAM models on CMP hardware. In Proceedings : IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008 USA: IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/IPDPS.2008.4536126
    Forsell, Martti. / On the performance and cost of some PRAM models on CMP hardware. Proceedings : IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008. USA : IEEE Institute of Electrical and Electronic Engineers , 2008.
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    Forsell, M 2008, On the performance and cost of some PRAM models on CMP hardware. in Proceedings : IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008. IEEE Institute of Electrical and Electronic Engineers , USA, IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, FL, United States, 14/04/08. https://doi.org/10.1109/IPDPS.2008.4536126

    On the performance and cost of some PRAM models on CMP hardware. / Forsell, Martti.

    Proceedings : IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008. USA : IEEE Institute of Electrical and Electronic Engineers , 2008.

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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    Forsell M. On the performance and cost of some PRAM models on CMP hardware. In Proceedings : IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008. USA: IEEE Institute of Electrical and Electronic Engineers . 2008 https://doi.org/10.1109/IPDPS.2008.4536126