Abstract
The Parallel Random Access Machine is a very strong model
of parallel computing that has resisted cost-effective
implementation attempts for decades. Recently, the
development of VLSI technology has provided means for
indirect on-chip implementation, but there are different
variants of the PRAM model that provide different
performance, area and power figures and it is not known
how their implementations compare to each others. In this
paper we measure the performance and estimate the cost of
practical implementations of four PRAM models including
EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full
Arbitrary Multioperation CRCW on our Eclipse chip
multiprocessor framework. Interestingly, the most
powerful model shows the lowest relative cost and highest
performance/area and performance/power figures.
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008 |
| Place of Publication | USA |
| Publisher | IEEE Institute of Electrical and Electronic Engineers |
| Number of pages | 8 |
| ISBN (Print) | 978-1-4244-1693-6, 978-1-4244-1694-3 |
| DOIs | |
| Publication status | Published - 2008 |
| MoE publication type | A4 Article in a conference publication |
| Event | IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008 - Miami, FL, United States Duration: 14 Apr 2008 → 18 Apr 2008 |
Conference
| Conference | IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008 |
|---|---|
| Abbreviated title | IPDPS 2008 |
| Country/Territory | United States |
| City | Miami, FL |
| Period | 14/04/08 → 18/04/08 |
Keywords
- parallel computing
- performance modeling
- silicon area modeling
- power consumption modeling
- PRAM
- CMP