Optimisation of add-on NPN transistor for a CMOS process

The objective of this research was to add an npn-bipolar transistor for a CMOS process. This was to be done with minimal additional process steps and without changing any existing CMOS parameters. The minimum line width of the process was 1.2µm, the wafers were p-type and 100mm in diameter and no epitaxial or polysilicon layers were used. To minimise the additional process steps a triple diffused transistor was selected as the basis of the research. The emitter was formed from a diffusion contacting NMOSFET source and drain to aluminium. As collector diffusion two approaches were investigated the pnpbipolar transistors isolation nwell and the PMOSFET n-well. The only additional step to the CMOS process due to the npn-transistor fabrication resulted from the formation of base diffusion. The specifications for the npn-transistor were 80 for the current gain, 100V for the early voltage and 60MHz for the transition frequency at 1µA collector current. Four different transistor structures were investigated two octagonal transistors having either emitter or base in the centre and two minimum area rectangular transistors having either base or emitter in the middle. The octagonal transistor having the emitter in the centre was chosen as the basis of simulations. It was first simulated with a device simulator. Next combined process and device simulations were done. Based on simulation results different processes were tested on wafers. Only the octagonal transistor having the emitter in the middle satisfied the specifications when a pnp isolation n-well was used as a collector.