Optimisation of add-on NPN transistor for a CMOS process

Artto Aurola (Corresponding Author), Hannu Ronkainen, Joni Mellin

    Research output: Contribution to journalArticleScientificpeer-review

    Abstract

    The objective of this research was to add an npn-bipolar transistor for a CMOS process. This was to be done with minimal additional process steps and without changing any existing CMOS parameters. The minimum line width of the process was 1.2µm, the wafers were p-type and 100mm in diameter and no epitaxial or polysilicon layers were used. To minimise the additional process steps a triple diffused transistor was selected as the basis of the research. The emitter was formed from a diffusion contacting NMOSFET source and drain to aluminium. As collector diffusion two approaches were investigated the pnpbipolar transistors isolation nwell and the PMOSFET n-well. The only additional step to the CMOS process due to the npn-transistor fabrication resulted from the formation of base diffusion. The specifications for the npn-transistor were 80 for the current gain, 100V for the early voltage and 60MHz for the transition frequency at 1µA collector current. Four different transistor structures were investigated two octagonal transistors having either emitter or base in the centre and two minimum area rectangular transistors having either base or emitter in the middle. The octagonal transistor having the emitter in the centre was chosen as the basis of simulations. It was first simulated with a device simulator. Next combined process and device simulations were done. Based on simulation results different processes were tested on wafers. Only the octagonal transistor having the emitter in the middle satisfied the specifications when a pnp isolation n-well was used as a collector.
    Original languageEnglish
    Pages (from-to)100 - 106
    Number of pages7
    JournalPhysica Scripta
    VolumeT114
    DOIs
    Publication statusPublished - 2004
    MoE publication typeA1 Journal article-refereed
    Event20th Nordic Semiconductor Meeting, NSM20 - Tampere, Finland
    Duration: 25 Aug 200327 Aug 2003

    Fingerprint

    CMOS
    transistors
    optimization
    Optimization
    emitters
    Wafer
    accumulators
    Isolation
    Specification
    Device Simulation
    specifications
    isolation
    Process Simulation
    Linewidth
    wafers
    Aluminum
    Fabrication
    Simulation
    Simulator
    simulation

    Cite this

    Aurola, Artto ; Ronkainen, Hannu ; Mellin, Joni. / Optimisation of add-on NPN transistor for a CMOS process. In: Physica Scripta. 2004 ; Vol. T114. pp. 100 - 106.
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    abstract = "The objective of this research was to add an npn-bipolar transistor for a CMOS process. This was to be done with minimal additional process steps and without changing any existing CMOS parameters. The minimum line width of the process was 1.2µm, the wafers were p-type and 100mm in diameter and no epitaxial or polysilicon layers were used. To minimise the additional process steps a triple diffused transistor was selected as the basis of the research. The emitter was formed from a diffusion contacting NMOSFET source and drain to aluminium. As collector diffusion two approaches were investigated the pnpbipolar transistors isolation nwell and the PMOSFET n-well. The only additional step to the CMOS process due to the npn-transistor fabrication resulted from the formation of base diffusion. The specifications for the npn-transistor were 80 for the current gain, 100V for the early voltage and 60MHz for the transition frequency at 1µA collector current. Four different transistor structures were investigated two octagonal transistors having either emitter or base in the centre and two minimum area rectangular transistors having either base or emitter in the middle. The octagonal transistor having the emitter in the centre was chosen as the basis of simulations. It was first simulated with a device simulator. Next combined process and device simulations were done. Based on simulation results different processes were tested on wafers. Only the octagonal transistor having the emitter in the middle satisfied the specifications when a pnp isolation n-well was used as a collector.",
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    Optimisation of add-on NPN transistor for a CMOS process. / Aurola, Artto (Corresponding Author); Ronkainen, Hannu; Mellin, Joni.

    In: Physica Scripta, Vol. T114, 2004, p. 100 - 106.

    Research output: Contribution to journalArticleScientificpeer-review

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