Outline of RISC-based core for multicore on chip processor architecture supporting moving threads

Jani Paakkulainen, Juha-Matti Mäkelä, Ville Leppänen, Martti Forsell

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

Programming multicore systems is currently considered very difficult. One reason is that those are mostly constructed from the hardware point of view. Many of the processor core design solutions in contemporary constructions emphasize execution speed of a single thread. Since the memory access delay is the real bottleneck, such techniques often aim at maximizing cache hits by programmer guided locality of memory references and prefetching memory locations, etc. In this paper, we consider constructing processor core solutions that support easy-to-use programming approach based on the PRAM model. Specifically, we consider a processor core design of a multicore system, where the aim is to amortize the memory access delays by having multiple simultaneuous executable software threads per each processor core. The core switches the executed extremely light-weight thread at each step, and thus the core can wait for pending memory requests to complete without any penalty (as long as its has non-blocked threads). Moreover, we consider the core to support moving threads paradigm instead of traditional moving data paradigm. We present an outline of such a processor core architecture, where we change the traditional pipelined execution model of RISC.
Original languageEnglish
Title of host publicationProceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
EditorsBoris Rachev
PublisherAssociation for Computing Machinery ACM
PagesI.51-I.56
ISBN (Electronic)978-1-60558-986-2
DOIs
Publication statusPublished - 2009
MoE publication typeA4 Article in a conference publication
EventInternational Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, CompSysTech'09 - Ruse, Bulgaria
Duration: 18 Jun 200919 Jun 2009

Conference

ConferenceInternational Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, CompSysTech'09
Abbreviated titleCompSysTech'09
CountryBulgaria
CityRuse
Period18/06/0919/06/09

Fingerprint

Reduced instruction set computing
Program processors
Data storage equipment
Multicore programming
Switches
Hardware

Keywords

  • Parallel computing
  • moving threads
  • processor architecture
  • PRAM

Cite this

Paakkulainen, J., Mäkelä, J-M., Leppänen, V., & Forsell, M. (2009). Outline of RISC-based core for multicore on chip processor architecture supporting moving threads. In B. Rachev (Ed.), Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing (pp. I.51-I.56). Association for Computing Machinery ACM. https://doi.org/10.1145/1731740.1731753
Paakkulainen, Jani ; Mäkelä, Juha-Matti ; Leppänen, Ville ; Forsell, Martti. / Outline of RISC-based core for multicore on chip processor architecture supporting moving threads. Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing . editor / Boris Rachev. Association for Computing Machinery ACM, 2009. pp. I.51-I.56
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abstract = "Programming multicore systems is currently considered very difficult. One reason is that those are mostly constructed from the hardware point of view. Many of the processor core design solutions in contemporary constructions emphasize execution speed of a single thread. Since the memory access delay is the real bottleneck, such techniques often aim at maximizing cache hits by programmer guided locality of memory references and prefetching memory locations, etc. In this paper, we consider constructing processor core solutions that support easy-to-use programming approach based on the PRAM model. Specifically, we consider a processor core design of a multicore system, where the aim is to amortize the memory access delays by having multiple simultaneuous executable software threads per each processor core. The core switches the executed extremely light-weight thread at each step, and thus the core can wait for pending memory requests to complete without any penalty (as long as its has non-blocked threads). Moreover, we consider the core to support moving threads paradigm instead of traditional moving data paradigm. We present an outline of such a processor core architecture, where we change the traditional pipelined execution model of RISC.",
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Paakkulainen, J, Mäkelä, J-M, Leppänen, V & Forsell, M 2009, Outline of RISC-based core for multicore on chip processor architecture supporting moving threads. in B Rachev (ed.), Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing . Association for Computing Machinery ACM, pp. I.51-I.56, International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, CompSysTech'09, Ruse, Bulgaria, 18/06/09. https://doi.org/10.1145/1731740.1731753

Outline of RISC-based core for multicore on chip processor architecture supporting moving threads. / Paakkulainen, Jani; Mäkelä, Juha-Matti; Leppänen, Ville; Forsell, Martti.

Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing . ed. / Boris Rachev. Association for Computing Machinery ACM, 2009. p. I.51-I.56.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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Paakkulainen J, Mäkelä J-M, Leppänen V, Forsell M. Outline of RISC-based core for multicore on chip processor architecture supporting moving threads. In Rachev B, editor, Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing . Association for Computing Machinery ACM. 2009. p. I.51-I.56 https://doi.org/10.1145/1731740.1731753