Parallel application development scheme for general purpose NOCs

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    Abstract

    In this paper we propose a parallel application development scheme for general purpose networks on chip (NOC). The scheme includes a strong computing model supporting explicit thread-level parallelism and instruction-level parallelism (ILP), an easy to migrate parallel programming language, a virtual ILP optimizer supporting exploitation of the ILP model, and a streamlined software development flow. We have implemented the scheme for our Eclipse architecture and give an application example.
    Original languageEnglish
    Title of host publicationProceedings of the 2005 ECTI International Conference
    PublisherElectrical Engineering/Electronics, Computer, Communications and Information Technology Association (ECTI)
    Pages819-822
    ISBN (Print)974-466-047-3
    Publication statusPublished - 2005
    MoE publication typeA4 Article in a conference publication
    EventInternational Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005 - Pattaya, Thailand
    Duration: 12 May 200513 May 2005

    Conference

    ConferenceInternational Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005
    Abbreviated titleECTI 2005
    CountryThailand
    CityPattaya
    Period12/05/0513/05/05

    Keywords

    • parallel computing
    • application development
    • networks on chip

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  • Cite this

    Forsell, M. (2005). Parallel application development scheme for general purpose NOCs. In Proceedings of the 2005 ECTI International Conference (pp. 819-822). Electrical Engineering/Electronics, Computer, Communications and Information Technology Association (ECTI).