Abstract
In this paper we propose a parallel application development scheme for general purpose networks on chip (NOC). The scheme includes a strong computing model supporting explicit thread-level parallelism and instruction-level parallelism (ILP), an easy to migrate parallel programming language, a virtual ILP optimizer supporting exploitation of the ILP model, and a streamlined software development flow. We have implemented the scheme for our Eclipse architecture and give an application example.
| Original language | English |
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| Title of host publication | Proceedings of the 2005 ECTI International Conference |
| Publisher | Electrical engineering/electronics, computer, communications and information technology association (ECTI) |
| Pages | 819-822 |
| ISBN (Print) | 974-466-047-3 |
| Publication status | Published - 2005 |
| MoE publication type | A4 Article in a conference publication |
| Event | International Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005 - Pattaya, Thailand Duration: 12 May 2005 → 13 May 2005 |
Conference
| Conference | International Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005 |
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| Abbreviated title | ECTI 2005 |
| Country/Territory | Thailand |
| City | Pattaya |
| Period | 12/05/05 → 13/05/05 |
Keywords
- parallel computing
- application development
- networks on chip