Parallel application development scheme for general purpose NOCs

Martti Forsell

Parallel application development scheme for general purpose NOCs

Martti Forsell

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

In this paper we propose a parallel application development scheme for general purpose networks on chip (NOC). The scheme includes a strong computing model supporting explicit thread-level parallelism and instruction-level parallelism (ILP), an easy to migrate parallel programming language, a virtual ILP optimizer supporting exploitation of the ILP model, and a streamlined software development flow. We have implemented the scheme for our Eclipse architecture and give an application example.

Original language	English
Title of host publication	Proceedings of the 2005 ECTI International Conference
Publisher	Electrical engineering/electronics, computer, communications and information technology association (ECTI)
Pages	819-822
ISBN (Print)	974-466-047-3
Publication status	Published - 2005
MoE publication type	A4 Article in a conference publication
Event	International Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005 - Pattaya, Thailand Duration: 12 May 2005 → 13 May 2005

Conference

Conference	International Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005
Abbreviated title	ECTI 2005
Country/Territory	Thailand
City	Pattaya
Period	12/05/05 → 13/05/05

Keywords

parallel computing
application development
networks on chip

Cite this

@inproceedings{1a2da6e45d4246f9a9e7ef09ec024147,

title = "Parallel application development scheme for general purpose NOCs",

abstract = "In this paper we propose a parallel application development scheme for general purpose networks on chip (NOC). The scheme includes a strong computing model supporting explicit thread-level parallelism and instruction-level parallelism (ILP), an easy to migrate parallel programming language, a virtual ILP optimizer supporting exploitation of the ILP model, and a streamlined software development flow. We have implemented the scheme for our Eclipse architecture and give an application example.",

keywords = "parallel computing, application development, networks on chip",

author = "Martti Forsell",

year = "2005",

language = "English",

isbn = "974-466-047-3",

pages = "819--822",

booktitle = "Proceedings of the 2005 ECTI International Conference",

publisher = "Electrical engineering/electronics, computer, communications and information technology association (ECTI)",

address = "Thailand",

note = "International Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005, ECTI 2005 ; Conference date: 12-05-2005 Through 13-05-2005",

}

Forsell, M 2005, Parallel application development scheme for general purpose NOCs. in Proceedings of the 2005 ECTI International Conference. Electrical engineering/electronics, computer, communications and information technology association (ECTI), pp. 819-822, International Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005, Pattaya, Thailand, 12/05/05.

Parallel application development scheme for general purpose NOCs. / Forsell, Martti.
Proceedings of the 2005 ECTI International Conference. Electrical engineering/electronics, computer, communications and information technology association (ECTI), 2005. p. 819-822.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Parallel application development scheme for general purpose NOCs

AU - Forsell, Martti

PY - 2005

Y1 - 2005

N2 - In this paper we propose a parallel application development scheme for general purpose networks on chip (NOC). The scheme includes a strong computing model supporting explicit thread-level parallelism and instruction-level parallelism (ILP), an easy to migrate parallel programming language, a virtual ILP optimizer supporting exploitation of the ILP model, and a streamlined software development flow. We have implemented the scheme for our Eclipse architecture and give an application example.

AB - In this paper we propose a parallel application development scheme for general purpose networks on chip (NOC). The scheme includes a strong computing model supporting explicit thread-level parallelism and instruction-level parallelism (ILP), an easy to migrate parallel programming language, a virtual ILP optimizer supporting exploitation of the ILP model, and a streamlined software development flow. We have implemented the scheme for our Eclipse architecture and give an application example.

KW - parallel computing

KW - application development

KW - networks on chip

M3 - Conference article in proceedings

SN - 974-466-047-3

SP - 819

EP - 822

BT - Proceedings of the 2005 ECTI International Conference

PB - Electrical engineering/electronics, computer, communications and information technology association (ECTI)

T2 - International Conference on Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology, ECTI 2005

Y2 - 12 May 2005 through 13 May 2005

ER -

Parallel application development scheme for general purpose NOCs

Abstract

Conference

Keywords

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