Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architecture

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    2 Citations (Scopus)

    Abstract

    In this paper we present an analytical performance, area and power (PAP) model for a class of mesh-based emulated shared memory (ESM) chip multiprocessor (CMP) architectures, which are promising candidates for building blocks of general purpose and embedded parallel computing devices due to their efficiency in executing arbitrary computational loads and ease of programming achieved through utilizing strong models of computing. Based on the PAP model we commit a comprehensive design space exploration to to identify fundamental performance, area, and power trade-offs for the class of ESM CMP architectures employing incremental combinations of performance enhancement techniques
    Original languageEnglish
    Title of host publicationProceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008
    Place of PublicationLas Vegas, NV, USA
    PublisherCSREA Press
    Pages471-477
    Volume2
    ISBN (Print)1-60132-082-5, 1-60132-083-3
    Publication statusPublished - 2008
    MoE publication typeA4 Article in a conference publication
    EventInternational Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008 - Las Vegas, Nevada, United States
    Duration: 14 Jul 200817 Jul 2008

    Conference

    ConferenceInternational Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008
    Abbreviated titlePDPTA 2008
    CountryUnited States
    CityLas Vegas, Nevada
    Period14/07/0817/07/08

    Fingerprint

    Data storage equipment
    Parallel processing systems

    Keywords

    • CMP
    • parallel computing
    • PRAM
    • performance modeling
    • silicon area
    • power consumption

    Cite this

    Forsell, M., & Roivainen, J. (2008). Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architecture. In Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008 (Vol. 2, pp. 471-477). Las Vegas, NV, USA: CSREA Press.
    Forsell, Martti ; Roivainen, Jussi. / Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architecture. Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008. Vol. 2 Las Vegas, NV, USA : CSREA Press, 2008. pp. 471-477
    @inproceedings{a94b2bd06f324954a43383e1b51d3aff,
    title = "Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architecture",
    abstract = "In this paper we present an analytical performance, area and power (PAP) model for a class of mesh-based emulated shared memory (ESM) chip multiprocessor (CMP) architectures, which are promising candidates for building blocks of general purpose and embedded parallel computing devices due to their efficiency in executing arbitrary computational loads and ease of programming achieved through utilizing strong models of computing. Based on the PAP model we commit a comprehensive design space exploration to to identify fundamental performance, area, and power trade-offs for the class of ESM CMP architectures employing incremental combinations of performance enhancement techniques",
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    author = "Martti Forsell and Jussi Roivainen",
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    Forsell, M & Roivainen, J 2008, Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architecture. in Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008. vol. 2, CSREA Press, Las Vegas, NV, USA, pp. 471-477, International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008, Las Vegas, Nevada, United States, 14/07/08.

    Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architecture. / Forsell, Martti; Roivainen, Jussi.

    Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008. Vol. 2 Las Vegas, NV, USA : CSREA Press, 2008. p. 471-477.

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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    Forsell M, Roivainen J. Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architecture. In Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008. Vol. 2. Las Vegas, NV, USA: CSREA Press. 2008. p. 471-477