Abstract
In this paper we present an analytical performance, area
and power (PAP) model for a class of mesh-based emulated
shared memory (ESM) chip multiprocessor (CMP)
architectures, which are promising candidates for
building blocks of general purpose and embedded parallel
computing devices due to their efficiency in executing
arbitrary computational loads and ease of programming
achieved through utilizing strong models of computing.
Based on the PAP model we commit a comprehensive design
space exploration to to identify fundamental performance,
area, and power trade-offs for the class of ESM CMP
architectures employing incremental combinations of
performance enhancement techniques
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008 |
| Place of Publication | Las Vegas, NV, USA |
| Publisher | CSREA Press |
| Pages | 471-477 |
| Volume | 2 |
| ISBN (Print) | 1-60132-082-5, 1-60132-083-3 |
| Publication status | Published - 2008 |
| MoE publication type | A4 Article in a conference publication |
| Event | International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008 - Las Vegas, Nevada, United States Duration: 14 Jul 2008 → 17 Jul 2008 |
Conference
| Conference | International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2008 |
|---|---|
| Abbreviated title | PDPTA 2008 |
| Country/Territory | United States |
| City | Las Vegas, Nevada |
| Period | 14/07/08 → 17/07/08 |
Keywords
- CMP
- parallel computing
- PRAM
- performance modeling
- silicon area
- power consumption