Performance comparison of some shared memory organizations for 2D mesh-like NOCs

Martti Forsell

    Research output: Contribution to journalArticleScientificpeer-review

    6 Citations (Scopus)


    While the research community has already studied a considerable amount of techniques related to achieving high bandwidth, good reliability, low power consumption, certain quality of service in communication on networks on chip (NOC) especially with artificial communication patterns, a little attention has paid to the effects of memory organizations to performance of computing engines employing NOCs with real parallel workloads. In this paper we compare the performance of some shared memory organizations for chip multiprocessors (CMP) employing advanced homogeneous 2D-mesh-like NOCs and making use of emulated shared memory and non-uniform memory access models. The evaluated techniques range from applying different hashing functions to elimination methods of speed difference between processing resources and memories, and from access methods to latency hiding and concurrent memory access support techniques. Tests are performed on our CMP/NOC framework with simple but real parallel programs that can be directly used as building blocks of larger explicitly parallel applications.
    Original languageEnglish
    Pages (from-to)274-284
    Number of pages11
    JournalMicroprocessors and Microsystems
    Issue number2
    Publication statusPublished - 2011
    MoE publication typeA1 Journal article-refereed


    • NOC
    • CMP
    • memory organization
    • hashing
    • speed difference elimination
    • latency hiding
    • concurrent access


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