A physical model for vertical DMOS power transistors is presented. The model takes into account various short channel effects in the DMOS channel region and the velocity saturation and the exact device geometry in the drift region. The model, aimed at computer aided design of power integrated circuits, has been implemented in the APLAC circuit simulator. A good agreement between the measured and simulated results for vertical DMOSTs is demonstrated.
|Series||Physica Scripta T|
|Conference||16th Nordic Semiconductor Meeting|
|Period||12/06/94 → 15/06/94|