Physical modelling of vertical DMOS power transistors for circuit simulation

Mikael Andersson, Pekka Kuivalainen

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

4 Citations (Scopus)


A physical model for vertical DMOS power transistors is presented. The model takes into account various short channel effects in the DMOS channel region and the velocity saturation and the exact device geometry in the drift region. The model, aimed at computer aided design of power integrated circuits, has been implemented in the APLAC circuit simulator. A good agreement between the measured and simulated results for vertical DMOSTs is demonstrated.
Original languageEnglish
Title of host publicationProceedings of the 16th Nordic Semiconductor Meeting
EditorsHafliði Pétur Gíslason, Viðar Guðmundsson
Place of PublicationStockholm
PublisherRoyal Swedish Academy of Sciences
ISBN (Print)978-91-8730-821-5
Publication statusPublished - 1994
MoE publication typeA4 Article in a conference publication
Event16th Nordic Semiconductor Meeting - Laugarvatn, Iceland
Duration: 12 Jun 199415 Jun 1994

Publication series

SeriesPhysica Scripta T


Conference16th Nordic Semiconductor Meeting

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