Physical modelling of vertisal DMOS power transistors for circuit simulation

Mikael Andersson, Pekka Kuivalainen

Research output: Contribution to journalArticleScientificpeer-review


A physical model for vertical DMOS power transistors is presented. The model takes into account various short channel effects in the DMOS channel region and the velocity saturation and the exact device geometry in the drift region. The model, aimed at computer aided design of power integrated circuits, has been implemented in the APLAC circuit simulator. A good agreement between the measured and simulated results for vertical DMOSTs is demonstrated.
Original languageEnglish
Pages (from-to)157-158
Number of pages2
JournalPhysica Scripta
Issue numberT54
Publication statusPublished - 1994
MoE publication typeA1 Journal article-refereed

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