PillarHall - Lateral High Aspect Ratio Test Chips

    Research output: Contribution to conferenceConference AbstractScientificpeer-review

    Abstract

    The downscaling of future semiconductor devices with increasing 3D character leads to increasing demand for highly conformal thin films. Similarly, conformal deposition enables new opportunities in microelectromechanical systems (MEMS), photonics, and other material science applications. Although conformality is a core value proposition of Atomic Layer Deposition (ALD) and related thin film processing methods, it is challenging to measure and quantify, while standardized measurement methods do not exist. A potential approach to circumvent the challenge is a MEMS-based all-silicon lateral high aspect ratio (LHAR) test structure, PillarHall® developed at VTT [1]. The test chip is compatible with CMOS process lines and suitable for wide temperature range. Design of PillarHall® LHAR test structure consists of a lateral gap of 500 nm in height under a polysilicon silicon membrane, supported by silicon pillars. One test chip consists of multiple LHAR structures, where the gap length varies from 1 to 5000 µm, giving aspect ratios (length vs height) for the typical ~500 nm gap of 2:1 to 10 000:1. Silicon pillars provide dimensional accuracy by stabilizing the membrane roof. The pillars and additional distance indicator lines provide internal length scale for visual examination. PillarHall® Test Chips are available at VTT for applications and research cooperation. The test chips have been employed with good success in ALD, conformality metrology for baseline and figure-of-merits as well as comparative studies with vertical AR structures. Future opportunities are e.g in thin film process optimization and control & monitoring.
    Original languageEnglish
    Number of pages1
    Publication statusPublished - 20 Sep 2018
    MoE publication typeNot Eligible
    EventEuropean MEMS & Sensors Summit - Grenoble, France
    Duration: 19 Sep 201821 Sep 2018
    http://www1.semi.org/eu/mems-and-sensors-2018-program

    Conference

    ConferenceEuropean MEMS & Sensors Summit
    CountryFrance
    CityGrenoble
    Period19/09/1821/09/18
    Internet address

    Keywords

    • OtaNano

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  • Cite this

    Utriainen, M. (2018). PillarHall - Lateral High Aspect Ratio Test Chips. Abstract from European MEMS & Sensors Summit, Grenoble, France.