Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors

Martti Forsell, Jussi Roivainen, Ville Leppanen, Jesper Larsson Traff

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review


Scalability of performance and memory bandwidth over a wide variety of computational and memory access patterns are important goals of multicore processor design. Current commercial processor lines are, however, not succeeding well in meeting key requirements for efficient parallel execution in their small, entry-level designs nor tolerating increasing latency of shared memory accesses, retaining memory access bandwidth per core and keeping the cost of synchronization low as the number of processor cores increases towards high-end products. We have introduced the thick control flow processor architecture (TPA), which combines an advanced shared memory abstraction architecture with the thick control flow (TCF) programming scheme and shown that it can address these requirements in its entry-level configuration. In this paper, we study the performance and memory access scalability of TCF processors. For that we measure the execution time of a number of parallel kernel programs and access patterns over a range of TPA processor configurations and compare them against each other and Intel Skylake-class client and server processors. The results indicate excellent scaling in both execution speed of kernels and bandwidth of memory access.

Original languageEnglish
Title of host publication2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings
EditorsJari Nurmi, Peeter Ellervee, Peter Koch, Farshad Moradi, Ming Shen
PublisherIEEE Institute of Electrical and Electronic Engineers
ISBN (Electronic)9798350337570
Publication statusPublished - 2023
MoE publication typeA4 Article in a conference publication
Event9th IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Aalborg, Denmark
Duration: 31 Oct 20231 Nov 2023


Conference9th IEEE Nordic Circuits and Systems Conference, NorCAS 2023


This work was supported by VTT and done in collaboration with the European Union Horizon 2020 research and innovation programme in project DEDICAT 6G under Grant Agreement No. 101016499. The contents of this publication are the sole responsibility of the authors and do not in any way reflect the views of the EU.


  • memory access
  • parallel computing
  • performance scalablity
  • processor architecture
  • TCF


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