Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

Vesa Vuorinen, Glenn Ross, Heikki Viljanen, James Decker, Mervi Paulasto-Krockel

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.
Original languageEnglish
Title of host publication 2018 7th Electronic System-Integration Technology Conference (ESTC)
PublisherInstitute of Electrical and Electronic Engineers IEEE
Number of pages6
ISBN (Electronic)978-1-5386-6814-6, 978-1-5386-6813-9
ISBN (Print)978-1-5386-6815-3
DOIs
Publication statusPublished - 2018
MoE publication typeNot Eligible
Event7th Electronic System-Integration Technology Conference, ESTC 2018 - Westin Bellevue Hotel and Conference Center Dresden, Dresden, Germany
Duration: 18 Sep 201821 Sep 2018
Conference number: 7

Conference

Conference7th Electronic System-Integration Technology Conference, ESTC 2018
Abbreviated titleESTC 2018
CountryGermany
CityDresden
Period18/09/1821/09/18

Fingerprint

Interdiffusion (solids)
Polysilicon
MEMS
Silicon
Liquids
Metallurgy
Metallizing
Failure analysis
Packaging

Cite this

Vuorinen, V., Ross, G., Viljanen, H., Decker, J., & Paulasto-Krockel, M. (2018). Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. In 2018 7th Electronic System-Integration Technology Conference (ESTC) [8546398] Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/ESTC.2018.8546398
Vuorinen, Vesa ; Ross, Glenn ; Viljanen, Heikki ; Decker, James ; Paulasto-Krockel, Mervi. / Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. 2018 7th Electronic System-Integration Technology Conference (ESTC). Institute of Electrical and Electronic Engineers IEEE, 2018.
@inproceedings{1c73bbf65fd5484f914ec8417bffa30a,
title = "Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS",
abstract = "The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.",
author = "Vesa Vuorinen and Glenn Ross and Heikki Viljanen and James Decker and Mervi Paulasto-Krockel",
year = "2018",
doi = "10.1109/ESTC.2018.8546398",
language = "English",
isbn = "978-1-5386-6815-3",
booktitle = "2018 7th Electronic System-Integration Technology Conference (ESTC)",
publisher = "Institute of Electrical and Electronic Engineers IEEE",
address = "United States",

}

Vuorinen, V, Ross, G, Viljanen, H, Decker, J & Paulasto-Krockel, M 2018, Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. in 2018 7th Electronic System-Integration Technology Conference (ESTC)., 8546398, Institute of Electrical and Electronic Engineers IEEE, 7th Electronic System-Integration Technology Conference, ESTC 2018, Dresden, Germany, 18/09/18. https://doi.org/10.1109/ESTC.2018.8546398

Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. / Vuorinen, Vesa; Ross, Glenn; Viljanen, Heikki; Decker, James; Paulasto-Krockel, Mervi.

2018 7th Electronic System-Integration Technology Conference (ESTC). Institute of Electrical and Electronic Engineers IEEE, 2018. 8546398.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

TY - GEN

T1 - Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

AU - Vuorinen, Vesa

AU - Ross, Glenn

AU - Viljanen, Heikki

AU - Decker, James

AU - Paulasto-Krockel, Mervi

PY - 2018

Y1 - 2018

N2 - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

AB - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

UR - http://www.scopus.com/inward/record.url?scp=85060057433&partnerID=8YFLogxK

U2 - 10.1109/ESTC.2018.8546398

DO - 10.1109/ESTC.2018.8546398

M3 - Conference article in proceedings

SN - 978-1-5386-6815-3

BT - 2018 7th Electronic System-Integration Technology Conference (ESTC)

PB - Institute of Electrical and Electronic Engineers IEEE

ER -

Vuorinen V, Ross G, Viljanen H, Decker J, Paulasto-Krockel M. Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. In 2018 7th Electronic System-Integration Technology Conference (ESTC). Institute of Electrical and Electronic Engineers IEEE. 2018. 8546398 https://doi.org/10.1109/ESTC.2018.8546398