Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

Vesa Vuorinen; Glenn Ross; Heikki Viljanen; James Decker; Mervi Paulasto-Krockel

doi:10.1109/ESTC.2018.8546398

Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

Vesa Vuorinen, Glenn Ross, Heikki Viljanen, James Decker, Mervi Paulasto-Krockel

Aalto University

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

Original language	English
Title of host publication	2018 7th Electronic System-Integration Technology Conference (ESTC)
Publisher	IEEE Institute of Electrical and Electronic Engineers
Number of pages	6
ISBN (Electronic)	978-1-5386-6814-6, 978-1-5386-6813-9
ISBN (Print)	978-1-5386-6815-3
DOIs	https://doi.org/10.1109/ESTC.2018.8546398
Publication status	Published - 2018
MoE publication type	Not Eligible
Event	7th Electronic System-Integration Technology Conference, ESTC 2018 - Westin Bellevue Hotel and Conference Center Dresden, Dresden, Germany Duration: 18 Sept 2018 → 21 Sept 2018 Conference number: 7

Conference

Conference	7th Electronic System-Integration Technology Conference, ESTC 2018
Abbreviated title	ESTC 2018
Country/Territory	Germany
City	Dresden
Period	18/09/18 → 21/09/18

Access to Document

10.1109/ESTC.2018.8546398

Cite this

@inproceedings{1c73bbf65fd5484f914ec8417bffa30a,

title = "Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS",

abstract = "The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.",

author = "Vesa Vuorinen and Glenn Ross and Heikki Viljanen and James Decker and Mervi Paulasto-Krockel",

year = "2018",

doi = "10.1109/ESTC.2018.8546398",

language = "English",

isbn = "978-1-5386-6815-3",

booktitle = "2018 7th Electronic System-Integration Technology Conference (ESTC)",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "7th Electronic System-Integration Technology Conference, ESTC 2018, ESTC 2018 ; Conference date: 18-09-2018 Through 21-09-2018",

}

Vuorinen, V, Ross, G, Viljanen, H, Decker, J & Paulasto-Krockel, M 2018, Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. in 2018 7th Electronic System-Integration Technology Conference (ESTC)., 8546398, IEEE Institute of Electrical and Electronic Engineers, 7th Electronic System-Integration Technology Conference, ESTC 2018, Dresden, Saxony, Germany, 18/09/18. https://doi.org/10.1109/ESTC.2018.8546398

Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS. / Vuorinen, Vesa; Ross, Glenn; Viljanen, Heikki et al.
2018 7th Electronic System-Integration Technology Conference (ESTC). IEEE Institute of Electrical and Electronic Engineers, 2018. 8546398.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

AU - Vuorinen, Vesa

AU - Ross, Glenn

AU - Viljanen, Heikki

AU - Decker, James

AU - Paulasto-Krockel, Mervi

N1 - Conference code: 7

PY - 2018

Y1 - 2018

N2 - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

AB - The objective of this study was to develop a fully integrated process for wafer level MEMS packaging utilizing PolySi through silicon via (TSV) capped MEMS devices. First, interconnection metallurgy and Solid Liquid Interdiffusion (SLID) bonding process was optimized. Then sc.“vias before bonding” capping process and contact metallizations for Poly-Si TSVs were developed. Finally, the process integration was demonstrated by using piezoelectrically driven MEMSactuators. However, several design and manufacturing related challenges were observed and detailed failure analysis were carried out to resolve these problems.

UR - http://www.scopus.com/inward/record.url?scp=85060057433&partnerID=8YFLogxK

U2 - 10.1109/ESTC.2018.8546398

DO - 10.1109/ESTC.2018.8546398

M3 - Conference article in proceedings

SN - 978-1-5386-6815-3

BT - 2018 7th Electronic System-Integration Technology Conference (ESTC)

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 7th Electronic System-Integration Technology Conference, ESTC 2018

Y2 - 18 September 2018 through 21 September 2018

ER -

Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this