Prototyping the MBTAC Processor for the REPLICA CMP

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    3 Citations (Scopus)

    Abstract

    Current chip multiprocessors (CMP) have mostly been designed by replicating sequential/single core processors and providing some support for operating them with a shared memory. As a result of this, they define asynchronous compu- tational model of threads, often require maximizing the local- ity of memory references to get decent performance, and fea- ture high intercommunication overheads, that make parallel programming tedious for general purpose functionalities. Most of these problems can be eliminated by designing the processors architecture for scalable general purpose comput- ing from the very beginning like done in processors for config- urable emulated shared memory (CESM) CMPs. They pro- vide support for machine instruction-level synchronization, make use of multithreading to support latency-insensitive computation, and promote the concept of uniform synchro- nous shared memory for easy variable allocation and conven- ient data exchange. In our earlier work we have proposed the first CESM architecture TOTAL ECLIPSE composed of early MBTAC processors making use of very low-overhead multi- threading, parallel computing savvy functional unit organiza- tion, support for fast synchronization between the instruc- tions and threads, and highly efficient multioperations. Unfortunately, certain key parts of these processors turned out to be hardly implementable and overall they lacked sup- port for ordered multiprefix operations and full configurabil- ity of the CESM scheme. In this paper we introduce a new fully configurable version of the MBTAC processor for our new REPLICA CESM architecture and the first FPGA imple- mentations of it. To evaluate it, we execute short test programs on it and compare it preliminary against Intel Core i7 and DLX processors. Our FPGA design flow and testing approach are described.
    Original languageEnglish
    Title of host publicationProceedings
    Subtitle of host publicationIEEE International Parallel & Distributed Processing Symposium Workshops, IPDPSW 2014
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages709-716
    ISBN (Electronic)978-1-4799-4116-2
    ISBN (Print)978-1-4799-4117-9
    DOIs
    Publication statusPublished - 2014
    MoE publication typeA4 Article in a conference publication
    Event28th IEEE International Parallel & Distributed Processing Symposium Workshops, IPDPSW 2014 - Phoenix, Arizona, United States
    Duration: 19 May 201423 May 2014
    Conference number: 28th

    Conference

    Conference28th IEEE International Parallel & Distributed Processing Symposium Workshops, IPDPSW 2014
    Abbreviated titleIPDPSW 2014
    CountryUnited States
    CityPhoenix, Arizona
    Period19/05/1423/05/14

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