Realising constant time parallel algorithms with active memory modules

    Research output: Contribution to journalArticleScientificpeer-review

    Abstract

    Recent advances in emulated shared memory architectures have made it possible to exploit the full power of a scalable parallel hardware in an easy-to-program form. Unfortunately, the obtained model of computing does not allow efficient parallel access to a single memory cell leaving the lower bound of the execution time of many important parallel algorithms logarithmic. In this paper, we describe a simple active memory based modification on memory module architecture that eliminates this limitation in many cases. Both algorithmic and real life examples are given. The resulting architecture can be used as a scalable processing infrastructure building block for general purpose applications like e-business, e-education, e-science, and e-medicine on the internet.
    Original languageEnglish
    Pages (from-to)255 - 263
    Number of pages9
    JournalInternational Journal of Electronic Business
    Volume3
    Issue number3-4
    DOIs
    Publication statusPublished - 2005
    MoE publication typeA1 Journal article-refereed

    Keywords

    • Computer architecture
    • parallel computing
    • active memory
    • memory modules
    • memory systems
    • models of computing
    • parallel algorithms
    • infrastructure for e-business

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