Realising constant time parallel algorithms with active memory modules

Recent advances in emulated shared memory architectures have made it possible to exploit the full power of a scalable parallel hardware in an easy-to-program form. Unfortunately, the obtained model of computing does not allow efficient parallel access to a single memory cell leaving the lower bound of the execution time of many important parallel algorithms logarithmic. In this paper, we describe a simple active memory based modification on memory module architecture that eliminates this limitation in many cases. Both algorithmic and real life examples are given. The resulting architecture can be used as a scalable processing infrastructure building block for general purpose applications like e-business, e-education, e-science, and e-medicine on the internet.