Realizing multioperations for step cached MP-SOCs

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    12 Citations (Scopus)

    Abstract

    Recent advances in shared memory multiprocessor system-on-a-chip (MP-SOC) architectures include using special step caches to efficiently implement concurrent read concurrent write memory access. Unfortunately the existing step cache techniques do not support multioperations that can be used to speed up execution of a number of parallel algorithms by a logarithmic factor. In this paper we propose an architectural technique for implementing multioperations on step cached MP-SOCs even if the associativity of caches is limited. The technique is based on simple active memory units, faster memory modules, and small processor-level memory blocks called scratchpads. We evaluate the performance and area requirements of the proposed technique on our parametrical MP-SOC framework. According to the evaluation the technique implements multioperations efficiently and provides a speed-up of 4.8-7.2 with respect to baseline step cached systems and a speed-up of 3.7-5.0 with respect to existing non-step cached systems with only a minor silicon area overhead.
    Original languageEnglish
    Title of host publication2006 International Symposium on System-on-Chip
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages77-82
    ISBN (Electronic)1-4244-0622-6
    ISBN (Print)1-4244-0621-8
    DOIs
    Publication statusPublished - 2006
    MoE publication typeA4 Article in a conference publication
    EventInternational Symposium on System-on-Chip, SOC 2006 - Tampere, Finland
    Duration: 11 Nov 200616 Nov 2006

    Conference

    ConferenceInternational Symposium on System-on-Chip, SOC 2006
    Abbreviated titleSOC 2006
    CountryFinland
    CityTampere
    Period11/11/0616/11/06

    Keywords

    • parallel computing
    • active memory
    • step caches
    • multioperation
    • PRAM
    • MP-SOC

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