Realizing multioperations for step cached MP-SOCs

Recent advances in shared memory multiprocessor system-on-a-chip (MP-SOC) architectures include using special step caches to efficiently implement concurrent read concurrent write memory access. Unfortunately the existing step cache techniques do not support multioperations that can be used to speed up execution of a number of parallel algorithms by a logarithmic factor. In this paper we propose an architectural technique for implementing multioperations on step cached MP-SOCs even if the associativity of caches is limited. The technique is based on simple active memory units, faster memory modules, and small processor-level memory blocks called scratchpads. We evaluate the performance and area requirements of the proposed technique on our parametrical MP-SOC framework. According to the evaluation the technique implements multioperations efficiently and provides a speed-up of 4.8-7.2 with respect to baseline step cached systems and a speed-up of 3.7-5.0 with respect to existing non-step cached systems with only a minor silicon area overhead.