REPLICA MBTAC: multithreaded dual-mode processor

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    1 Citation (Scopus)

    Abstract

    Prevailing trend in design of chip multiprocessors (CMP) has been that single-core processors are replicated. Therefore, they typically define asynchronous computational model, require heavily locality-aware memory allocation, and present high overheads in intercommunication. This kind of properties make parallel programming very challenging and prone to errors. We introduce our new dual-mode MultiBunched/Threaded Architecture with Chaining (MBTAC) processor core, the main building block of the REPLICA CMP. It provides a modern, sophisticated way for writing general purpose parallel programs backed up by native execution capabilities/realization of key concepts. These include support for cost-efficient machine instruction-level synchronization and uniform shared global memory for enabling easy-to-program memory allocation of data structures and data movement. MBTAC makes use of low-overhead thread-context switching solution; it has parallel computing savvy functional unit organization to exploit inter-thread instruction-level parallelism and highly efficient multioperations. To evaluate the goodness of our proposal, we implemented three MBTAC constellations featuring up to 2048 parallel threads on FPGA, compared it with respect to DLX and Intel’s Core i7 processors. The results point toward high performance in communication-intensive problems, simplified parallel programmability, and regular, implementation-friendly structure.

    Original languageEnglish
    Pages (from-to)1911-1933
    Number of pages23
    JournalThe Journal of Supercomputing
    Volume74
    Issue number5
    DOIs
    Publication statusPublished - 1 May 2018
    MoE publication typeA1 Journal article-refereed

    Keywords

    • Chaining of functional units
    • FPGA prototype
    • Multithreaded processor
    • NUMA mode
    • Parallelism
    • PRAM mode

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