REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor

Martti Forsell; Jussi Roivainen

doi:10.1109/ACSSC.2014.7094759

REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor

Martti Forsell, Jussi Roivainen

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

Processor-based solutions are getting increasingly popular over dedicated logic/accelerators among embedded system designers due to their flexibility and programmability. The drawbacks - weaker performance and higher power consumption - are usually compensated with multicore and application-specific technologies. Unfortunately, these optimizations - exploiting parallelism and heterogeneity - lead to direction that makes programming difficult and result to less flexible designs. REPLICA is VTT's effort to solve the performance and programmability problems of current multicore processors without tampering flexibility. For performance, it addresses the essence of parallel computing - cost-efficient synchronization, high intercommunication bandwidth and latency toleration - with a new collection of architectural techniques: multithreading, sparse/multimesh network-on-chip and wave-based synchronization. Programmability is made simple by supporting efficient execution of synchronous parallel algorithms and flexibility is provided with parametric nature of the architecture allowing for highly different configurations. In this paper we introduce a 2048-threaded 16-core prototype of the REPLICA chip multiprocessor. The main principles of the architecture as well as the structure of the prototype are explained. Preliminary comparison to current alternatives is given.

Original language	English
Title of host publication	Conference Record of The Forty-Eighth Asilomar Conference on Signals, Systems & Computers
Editors	Michael B. Matthews
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	1709-1713
Number of pages	5
ISBN (Electronic)	978-147998297-4
DOIs	https://doi.org/10.1109/ACSSC.2014.7094759
Publication status	Published - 2015
MoE publication type	Not Eligible
Event	48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 - Pacific Grove, United States Duration: 2 Nov 2014 → 5 Nov 2014

Conference

Conference	48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015
Country/Territory	United States
City	Pacific Grove
Period	2/11/14 → 5/11/14

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10.1109/ACSSC.2014.7094759

Cite this

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title = "REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor",

abstract = "Processor-based solutions are getting increasingly popular over dedicated logic/accelerators among embedded system designers due to their flexibility and programmability. The drawbacks - weaker performance and higher power consumption - are usually compensated with multicore and application-specific technologies. Unfortunately, these optimizations - exploiting parallelism and heterogeneity - lead to direction that makes programming difficult and result to less flexible designs. REPLICA is VTT's effort to solve the performance and programmability problems of current multicore processors without tampering flexibility. For performance, it addresses the essence of parallel computing - cost-efficient synchronization, high intercommunication bandwidth and latency toleration - with a new collection of architectural techniques: multithreading, sparse/multimesh network-on-chip and wave-based synchronization. Programmability is made simple by supporting efficient execution of synchronous parallel algorithms and flexibility is provided with parametric nature of the architecture allowing for highly different configurations. In this paper we introduce a 2048-threaded 16-core prototype of the REPLICA chip multiprocessor. The main principles of the architecture as well as the structure of the prototype are explained. Preliminary comparison to current alternatives is given.",

author = "Martti Forsell and Jussi Roivainen",

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address = "United States",

note = "48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 ; Conference date: 02-11-2014 Through 05-11-2014",

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Forsell, M & Roivainen, J 2015, REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. in MB Matthews (ed.), Conference Record of The Forty-Eighth Asilomar Conference on Signals, Systems & Computers., 7094759, IEEE Institute of Electrical and Electronic Engineers, pp. 1709-1713, 48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015, Pacific Grove, California, United States, 2/11/14. https://doi.org/10.1109/ACSSC.2014.7094759

REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. / Forsell, Martti; Roivainen, Jussi.
Conference Record of The Forty-Eighth Asilomar Conference on Signals, Systems & Computers. ed. / Michael B. Matthews. IEEE Institute of Electrical and Electronic Engineers, 2015. p. 1709-1713 7094759.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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AU - Roivainen, Jussi

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N2 - Processor-based solutions are getting increasingly popular over dedicated logic/accelerators among embedded system designers due to their flexibility and programmability. The drawbacks - weaker performance and higher power consumption - are usually compensated with multicore and application-specific technologies. Unfortunately, these optimizations - exploiting parallelism and heterogeneity - lead to direction that makes programming difficult and result to less flexible designs. REPLICA is VTT's effort to solve the performance and programmability problems of current multicore processors without tampering flexibility. For performance, it addresses the essence of parallel computing - cost-efficient synchronization, high intercommunication bandwidth and latency toleration - with a new collection of architectural techniques: multithreading, sparse/multimesh network-on-chip and wave-based synchronization. Programmability is made simple by supporting efficient execution of synchronous parallel algorithms and flexibility is provided with parametric nature of the architecture allowing for highly different configurations. In this paper we introduce a 2048-threaded 16-core prototype of the REPLICA chip multiprocessor. The main principles of the architecture as well as the structure of the prototype are explained. Preliminary comparison to current alternatives is given.

AB - Processor-based solutions are getting increasingly popular over dedicated logic/accelerators among embedded system designers due to their flexibility and programmability. The drawbacks - weaker performance and higher power consumption - are usually compensated with multicore and application-specific technologies. Unfortunately, these optimizations - exploiting parallelism and heterogeneity - lead to direction that makes programming difficult and result to less flexible designs. REPLICA is VTT's effort to solve the performance and programmability problems of current multicore processors without tampering flexibility. For performance, it addresses the essence of parallel computing - cost-efficient synchronization, high intercommunication bandwidth and latency toleration - with a new collection of architectural techniques: multithreading, sparse/multimesh network-on-chip and wave-based synchronization. Programmability is made simple by supporting efficient execution of synchronous parallel algorithms and flexibility is provided with parametric nature of the architecture allowing for highly different configurations. In this paper we introduce a 2048-threaded 16-core prototype of the REPLICA chip multiprocessor. The main principles of the architecture as well as the structure of the prototype are explained. Preliminary comparison to current alternatives is given.

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BT - Conference Record of The Forty-Eighth Asilomar Conference on Signals, Systems & Computers

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PB - IEEE Institute of Electrical and Electronic Engineers

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Y2 - 2 November 2014 through 5 November 2014

ER -

REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor

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