RISC-based moving threads multicore architecture

J.-M. Mäkelä, V. Leppänen, Martti Forsell

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific

    Abstract

    In this paper, we describe the architectural output of our 'Moving threads realization study' (MOTH) project, which is a RISC-based multicore architecture framework. Each fraction of the memory can be accesses only via a certain core, via its cache memory. This approach leads to moving light-weight threads but at the same time provides strong memory coherences as no main memory location is replicated to several caches. We describe the overall multicore architecture, but special emphasis is put on describing the functionality of individual RISC-based core
    Original languageEnglish
    Title of host publicationProceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11
    PublisherAssociation for Computing Machinery ACM
    Pages51-56
    ISBN (Print)978-1-4503-0917-2
    DOIs
    Publication statusPublished - 2011
    MoE publication typeB3 Non-refereed article in conference proceedings
    Event12th International Conference on Computer Systems and Technologies, CompSysTech'11 - Vienna, Austria
    Duration: 16 Jun 201117 Jun 2011

    Conference

    Conference12th International Conference on Computer Systems and Technologies, CompSysTech'11
    Abbreviated titleCompSysTech 2011
    CountryAustria
    CityVienna
    Period16/06/1117/06/11

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    Keywords

    • Moving threads
    • multithreading
    • parallel computing
    • processor architecture
    • RISC

    Cite this

    Mäkelä, J-M., Leppänen, V., & Forsell, M. (2011). RISC-based moving threads multicore architecture. In Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11 (pp. 51-56). Association for Computing Machinery ACM. https://doi.org/10.1145/2023607.2023617