RISC-based moving threads multicore architecture

J.-M. Mäkelä, V. Leppänen, Martti Forsell

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific

Abstract

In this paper, we describe the architectural output of our 'Moving threads realization study' (MOTH) project, which is a RISC-based multicore architecture framework. Each fraction of the memory can be accesses only via a certain core, via its cache memory. This approach leads to moving light-weight threads but at the same time provides strong memory coherences as no main memory location is replicated to several caches. We describe the overall multicore architecture, but special emphasis is put on describing the functionality of individual RISC-based core
Original languageEnglish
Title of host publicationProceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11
PublisherAssociation for Computing Machinery ACM
Pages51-56
ISBN (Print)978-1-4503-0917-2
DOIs
Publication statusPublished - 2011
MoE publication typeB3 Non-refereed article in conference proceedings
Event12th International Conference on Computer Systems and Technologies, CompSysTech'11 - Vienna, Austria
Duration: 16 Jun 201117 Jun 2011

Conference

Conference12th International Conference on Computer Systems and Technologies, CompSysTech'11
Abbreviated titleCompSysTech 2011
CountryAustria
CityVienna
Period16/06/1117/06/11

Fingerprint

Reduced instruction set computing
Data storage equipment
Cache memory

Keywords

  • Moving threads
  • multithreading
  • parallel computing
  • processor architecture
  • RISC

Cite this

Mäkelä, J-M., Leppänen, V., & Forsell, M. (2011). RISC-based moving threads multicore architecture. In Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11 (pp. 51-56). Association for Computing Machinery ACM. https://doi.org/10.1145/2023607.2023617
Mäkelä, J.-M. ; Leppänen, V. ; Forsell, Martti. / RISC-based moving threads multicore architecture. Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11 . Association for Computing Machinery ACM, 2011. pp. 51-56
@inproceedings{d365c3bad3594be4aa98be889d35fe48,
title = "RISC-based moving threads multicore architecture",
abstract = "In this paper, we describe the architectural output of our 'Moving threads realization study' (MOTH) project, which is a RISC-based multicore architecture framework. Each fraction of the memory can be accesses only via a certain core, via its cache memory. This approach leads to moving light-weight threads but at the same time provides strong memory coherences as no main memory location is replicated to several caches. We describe the overall multicore architecture, but special emphasis is put on describing the functionality of individual RISC-based core",
keywords = "Moving threads, multithreading, parallel computing, processor architecture, RISC",
author = "J.-M. M{\"a}kel{\"a} and V. Lepp{\"a}nen and Martti Forsell",
year = "2011",
doi = "10.1145/2023607.2023617",
language = "English",
isbn = "978-1-4503-0917-2",
pages = "51--56",
booktitle = "Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11",
publisher = "Association for Computing Machinery ACM",
address = "United States",

}

Mäkelä, J-M, Leppänen, V & Forsell, M 2011, RISC-based moving threads multicore architecture. in Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11 . Association for Computing Machinery ACM, pp. 51-56, 12th International Conference on Computer Systems and Technologies, CompSysTech'11, Vienna, Austria, 16/06/11. https://doi.org/10.1145/2023607.2023617

RISC-based moving threads multicore architecture. / Mäkelä, J.-M.; Leppänen, V.; Forsell, Martti.

Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11 . Association for Computing Machinery ACM, 2011. p. 51-56.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific

TY - GEN

T1 - RISC-based moving threads multicore architecture

AU - Mäkelä, J.-M.

AU - Leppänen, V.

AU - Forsell, Martti

PY - 2011

Y1 - 2011

N2 - In this paper, we describe the architectural output of our 'Moving threads realization study' (MOTH) project, which is a RISC-based multicore architecture framework. Each fraction of the memory can be accesses only via a certain core, via its cache memory. This approach leads to moving light-weight threads but at the same time provides strong memory coherences as no main memory location is replicated to several caches. We describe the overall multicore architecture, but special emphasis is put on describing the functionality of individual RISC-based core

AB - In this paper, we describe the architectural output of our 'Moving threads realization study' (MOTH) project, which is a RISC-based multicore architecture framework. Each fraction of the memory can be accesses only via a certain core, via its cache memory. This approach leads to moving light-weight threads but at the same time provides strong memory coherences as no main memory location is replicated to several caches. We describe the overall multicore architecture, but special emphasis is put on describing the functionality of individual RISC-based core

KW - Moving threads

KW - multithreading

KW - parallel computing

KW - processor architecture

KW - RISC

U2 - 10.1145/2023607.2023617

DO - 10.1145/2023607.2023617

M3 - Conference article in proceedings

SN - 978-1-4503-0917-2

SP - 51

EP - 56

BT - Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11

PB - Association for Computing Machinery ACM

ER -

Mäkelä J-M, Leppänen V, Forsell M. RISC-based moving threads multicore architecture. In Proceedings of the 12th International Conference on Computer Systems and Technologies, CompSysTech '11 . Association for Computing Machinery ACM. 2011. p. 51-56 https://doi.org/10.1145/2023607.2023617