Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2012 |
| Publisher | IEEE Institute of Electrical and Electronic Engineers |
| Pages | 35-38 |
| ISBN (Electronic) | 978-1-4673-1638-5 |
| ISBN (Print) | 978-1-4673-1635-4 |
| DOIs | |
| Publication status | Published - 2012 |
| MoE publication type | Not Eligible |
| Event | 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2012 - Taipei, Taiwan, Province of China Duration: 24 Oct 2012 → 26 Oct 2012 |
Conference
| Conference | 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2012 |
|---|---|
| Abbreviated title | IMPACT 2012 |
| Country | Taiwan, Province of China |
| City | Taipei |
| Period | 24/10/12 → 26/10/12 |
Fingerprint
Cite this
}
Role of process gases in making tapered through-silicon vias for 3D MEMS packaging. / Dixit, Preadeep; Vähänen, Sami; Salonen, Jaakko; Monnoyer, Philippe.
Proceedings: 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2012. IEEE Institute of Electrical and Electronic Engineers , 2012. p. 35-38.Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review
TY - GEN
T1 - Role of process gases in making tapered through-silicon vias for 3D MEMS packaging
AU - Dixit, Preadeep
AU - Vähänen, Sami
AU - Salonen, Jaakko
AU - Monnoyer, Philippe
PY - 2012
Y1 - 2012
N2 - This article report a continuous plasma etching process using SF 6/O2/Ar gases for fabricating 100 µm deep tapered through-silicon vias (TSV). The flow rates of the process gases were changed to study their individual effect on the profile angle, via depth, sidewall roughness, and sideways undercut of the tapered vias. Tapered vias having profile angles varying from 70° to 85° and smooth sidewalls were etched by balancing the chemically-assisted isotropic etching of F* radicals, passivation film by O2, and ion-assisted passivation etching. The flow rates of SF6 and O2 were found to be the important factors which determine the profile angle and via surface roughness. After considering the individual effects of each gas, an optimized etching recipe was fixed, which was used to etch 100 µm deep vias having a profile angle of 83°. Insulation and seed layers were deposited by conventional low-temperature processes. The tapered vias were then partially filled by copper electrodeposition and redistribution lines were formed. The electrical resistance of tapered TSVs was measured to be between 3-8 m for the majority of the TSVs.
AB - This article report a continuous plasma etching process using SF 6/O2/Ar gases for fabricating 100 µm deep tapered through-silicon vias (TSV). The flow rates of the process gases were changed to study their individual effect on the profile angle, via depth, sidewall roughness, and sideways undercut of the tapered vias. Tapered vias having profile angles varying from 70° to 85° and smooth sidewalls were etched by balancing the chemically-assisted isotropic etching of F* radicals, passivation film by O2, and ion-assisted passivation etching. The flow rates of SF6 and O2 were found to be the important factors which determine the profile angle and via surface roughness. After considering the individual effects of each gas, an optimized etching recipe was fixed, which was used to etch 100 µm deep vias having a profile angle of 83°. Insulation and seed layers were deposited by conventional low-temperature processes. The tapered vias were then partially filled by copper electrodeposition and redistribution lines were formed. The electrical resistance of tapered TSVs was measured to be between 3-8 m for the majority of the TSVs.
U2 - 10.1109/IMPACT.2012.6420230
DO - 10.1109/IMPACT.2012.6420230
M3 - Conference article in proceedings
SN - 978-1-4673-1635-4
SP - 35
EP - 38
BT - Proceedings
PB - IEEE Institute of Electrical and Electronic Engineers
ER -