Scalable fault-tolerant logic system based on regular array of locally interconnected gates

Jacek Flak, M. Laiho, A. Paasio

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    2 Citations (Scopus)

    Abstract

    This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices.
    The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.
    Original languageEnglish
    Title of host publicationProceedings
    Subtitle of host publication11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008
    Place of PublicationPiscataway, NJ, USA
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages116-119
    ISBN (Print)978-1-4244-2089-6, 978-1-4244-2090-2
    DOIs
    Publication statusPublished - 2008
    MoE publication typeA4 Article in a conference publication
    Event11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008 - Santiago de Compostela, Spain
    Duration: 14 Jul 200816 Jul 2008

    Conference

    Conference11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008
    Abbreviated titleCNNA 2008
    CountrySpain
    CitySantiago de Compostela
    Period14/07/0816/07/08

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    Cite this

    Flak, J., Laiho, M., & Paasio, A. (2008). Scalable fault-tolerant logic system based on regular array of locally interconnected gates. In Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008 (pp. 116-119). Piscataway, NJ, USA: IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/CNNA.2008.4588661
    Flak, Jacek ; Laiho, M. ; Paasio, A. / Scalable fault-tolerant logic system based on regular array of locally interconnected gates. Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. Piscataway, NJ, USA : IEEE Institute of Electrical and Electronic Engineers , 2008. pp. 116-119
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    Flak, J, Laiho, M & Paasio, A 2008, Scalable fault-tolerant logic system based on regular array of locally interconnected gates. in Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. IEEE Institute of Electrical and Electronic Engineers , Piscataway, NJ, USA, pp. 116-119, 11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008, Santiago de Compostela, Spain, 14/07/08. https://doi.org/10.1109/CNNA.2008.4588661

    Scalable fault-tolerant logic system based on regular array of locally interconnected gates. / Flak, Jacek; Laiho, M.; Paasio, A.

    Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. Piscataway, NJ, USA : IEEE Institute of Electrical and Electronic Engineers , 2008. p. 116-119.

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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    AB - This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.

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    Flak J, Laiho M, Paasio A. Scalable fault-tolerant logic system based on regular array of locally interconnected gates. In Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. Piscataway, NJ, USA: IEEE Institute of Electrical and Electronic Engineers . 2008. p. 116-119 https://doi.org/10.1109/CNNA.2008.4588661