Abstract
The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008 |
| Place of Publication | Piscataway, NJ, USA |
| Publisher | IEEE Institute of Electrical and Electronic Engineers |
| Pages | 116-119 |
| ISBN (Print) | 978-1-4244-2089-6, 978-1-4244-2090-2 |
| DOIs | |
| Publication status | Published - 2008 |
| MoE publication type | A4 Article in a conference publication |
| Event | 11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008 - Santiago de Compostela, Spain Duration: 14 Jul 2008 → 16 Jul 2008 |
Conference
| Conference | 11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008 |
|---|---|
| Abbreviated title | CNNA 2008 |
| Country | Spain |
| City | Santiago de Compostela |
| Period | 14/07/08 → 16/07/08 |
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Scalable fault-tolerant logic system based on regular array of locally interconnected gates. / Flak, Jacek; Laiho, M.; Paasio, A.
Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. Piscataway, NJ, USA : IEEE Institute of Electrical and Electronic Engineers , 2008. p. 116-119.Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review
TY - GEN
T1 - Scalable fault-tolerant logic system based on regular array of locally interconnected gates
AU - Flak, Jacek
AU - Laiho, M.
AU - Paasio, A.
PY - 2008
Y1 - 2008
N2 - This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.
AB - This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.
U2 - 10.1109/CNNA.2008.4588661
DO - 10.1109/CNNA.2008.4588661
M3 - Conference article in proceedings
SN - 978-1-4244-2089-6
SN - 978-1-4244-2090-2
SP - 116
EP - 119
BT - Proceedings
PB - IEEE Institute of Electrical and Electronic Engineers
CY - Piscataway, NJ, USA
ER -