Abstract
This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices.
The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.
The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.
Original language | English |
---|---|
Title of host publication | Proceedings |
Subtitle of host publication | 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008 |
Place of Publication | Piscataway, NJ, USA |
Publisher | IEEE Institute of Electrical and Electronic Engineers |
Pages | 116-119 |
ISBN (Print) | 978-1-4244-2089-6, 978-1-4244-2090-2 |
DOIs | |
Publication status | Published - 2008 |
MoE publication type | A4 Article in a conference publication |
Event | 11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008 - Santiago de Compostela, Spain Duration: 14 Jul 2008 → 16 Jul 2008 |
Conference
Conference | 11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008 |
---|---|
Abbreviated title | CNNA 2008 |
Country/Territory | Spain |
City | Santiago de Compostela |
Period | 14/07/08 → 16/07/08 |