Scalable fault-tolerant logic system based on regular array of locally interconnected gates

Jacek Flak, M. Laiho, A. Paasio

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

2 Citations (Scopus)

Abstract

This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices.
The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.
Original languageEnglish
Title of host publicationProceedings
Subtitle of host publication11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008
Place of PublicationPiscataway, NJ, USA
PublisherIEEE Institute of Electrical and Electronic Engineers
Pages116-119
ISBN (Print)978-1-4244-2089-6, 978-1-4244-2090-2
DOIs
Publication statusPublished - 2008
MoE publication typeA4 Article in a conference publication
Event11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008 - Santiago de Compostela, Spain
Duration: 14 Jul 200816 Jul 2008

Conference

Conference11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008
Abbreviated titleCNNA 2008
CountrySpain
CitySantiago de Compostela
Period14/07/0816/07/08

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Redundancy
Processing

Cite this

Flak, J., Laiho, M., & Paasio, A. (2008). Scalable fault-tolerant logic system based on regular array of locally interconnected gates. In Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008 (pp. 116-119). Piscataway, NJ, USA: IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/CNNA.2008.4588661
Flak, Jacek ; Laiho, M. ; Paasio, A. / Scalable fault-tolerant logic system based on regular array of locally interconnected gates. Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. Piscataway, NJ, USA : IEEE Institute of Electrical and Electronic Engineers , 2008. pp. 116-119
@inproceedings{9bcfd4a5b6854b98a78f56ed850e8d0a,
title = "Scalable fault-tolerant logic system based on regular array of locally interconnected gates",
abstract = "This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.",
author = "Jacek Flak and M. Laiho and A. Paasio",
year = "2008",
doi = "10.1109/CNNA.2008.4588661",
language = "English",
isbn = "978-1-4244-2089-6",
pages = "116--119",
booktitle = "Proceedings",
publisher = "IEEE Institute of Electrical and Electronic Engineers",
address = "United States",

}

Flak, J, Laiho, M & Paasio, A 2008, Scalable fault-tolerant logic system based on regular array of locally interconnected gates. in Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. IEEE Institute of Electrical and Electronic Engineers , Piscataway, NJ, USA, pp. 116-119, 11th International Workshop on Cellular Neural Networks and Their Applications, CNNA 2008, Santiago de Compostela, Spain, 14/07/08. https://doi.org/10.1109/CNNA.2008.4588661

Scalable fault-tolerant logic system based on regular array of locally interconnected gates. / Flak, Jacek; Laiho, M.; Paasio, A.

Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. Piscataway, NJ, USA : IEEE Institute of Electrical and Electronic Engineers , 2008. p. 116-119.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

TY - GEN

T1 - Scalable fault-tolerant logic system based on regular array of locally interconnected gates

AU - Flak, Jacek

AU - Laiho, M.

AU - Paasio, A.

PY - 2008

Y1 - 2008

N2 - This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.

AB - This paper presents a new approach towards fault-tolerant information processing. The proposed system combines different types of redundancy into a solution suitable for implementation with nanodevices. The architecture is based on regular array of locally interconnected processing elements (PE). The interconnections are binary programmable in order to achieve network versatility. The array can be divided into a set of segments in a flexible manner, providing a means for implementing functions with different levels of complexity and redundancy.

U2 - 10.1109/CNNA.2008.4588661

DO - 10.1109/CNNA.2008.4588661

M3 - Conference article in proceedings

SN - 978-1-4244-2089-6

SN - 978-1-4244-2090-2

SP - 116

EP - 119

BT - Proceedings

PB - IEEE Institute of Electrical and Electronic Engineers

CY - Piscataway, NJ, USA

ER -

Flak J, Laiho M, Paasio A. Scalable fault-tolerant logic system based on regular array of locally interconnected gates. In Proceedings: 11th International Workshop on Cellular Neural Networks and their Applications, CNNA 2008. Piscataway, NJ, USA: IEEE Institute of Electrical and Electronic Engineers . 2008. p. 116-119 https://doi.org/10.1109/CNNA.2008.4588661