Scalable general purpose CMP architecture

    Research output: Contribution to conferenceConference articleScientificpeer-review

    Abstract

    Due to inherent non-scalability of superscalar processors, processor manufacturers have switched to mul-ti-core or chip multiprocessor (CMP) engines utilizing the symmetrical multiprocessing (SMP) para-digm. Since it is expected that the number of cores per chip will fast increase to a level in which only a fraction of the total computational power can be allocated for a single computational task using SMP, better architectures and computing models with easy-to-use (parallel) programming languages and tools are required. In this presentation we will outline a scalable general purpose CMP architecture being de-veloped at VTT that allows a programmer to utilize fine-grained parallelism under a strong model of computing and to allocate the full computational power of the CMP to arbitrary workloads ranging from a single computational task to multiple independent parallel programs. We will focus on performance is-sues related on latest architectural additions including step cache-based support for concurrect read con-current write (CRCW) access and fast multioperations. According to our preliminary evaluation, good performance figures and scalability can be achieved with these techniques in executing parallel programs written with a high-level language and compiled with very early prototype tools.
    Original languageEnglish
    Publication statusPublished - 2006
    MoE publication typeNot Eligible
    EventScalable Approaches to High-Performance and High-Productivity Computing 2006, ScalPerf'06 - University of Padua, Bertinoro, Italy
    Duration: 3 Sep 20067 Sep 2006

    Conference

    ConferenceScalable Approaches to High-Performance and High-Productivity Computing 2006, ScalPerf'06
    Abbreviated titleScalPerf'06
    CountryItaly
    CityBertinoro
    Period3/09/067/09/06

    Fingerprint

    High level languages
    Parallel programming
    Computer programming languages
    Scalability
    Engines

    Keywords

    • parallel computing
    • computer architecture
    • scalability
    • computing model
    • CMP
    • CRCW PRAM

    Cite this

    Forsell, M. (2006). Scalable general purpose CMP architecture. Paper presented at Scalable Approaches to High-Performance and High-Productivity Computing 2006, ScalPerf'06, Bertinoro, Italy.
    Forsell, Martti. / Scalable general purpose CMP architecture. Paper presented at Scalable Approaches to High-Performance and High-Productivity Computing 2006, ScalPerf'06, Bertinoro, Italy.
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    abstract = "Due to inherent non-scalability of superscalar processors, processor manufacturers have switched to mul-ti-core or chip multiprocessor (CMP) engines utilizing the symmetrical multiprocessing (SMP) para-digm. Since it is expected that the number of cores per chip will fast increase to a level in which only a fraction of the total computational power can be allocated for a single computational task using SMP, better architectures and computing models with easy-to-use (parallel) programming languages and tools are required. In this presentation we will outline a scalable general purpose CMP architecture being de-veloped at VTT that allows a programmer to utilize fine-grained parallelism under a strong model of computing and to allocate the full computational power of the CMP to arbitrary workloads ranging from a single computational task to multiple independent parallel programs. We will focus on performance is-sues related on latest architectural additions including step cache-based support for concurrect read con-current write (CRCW) access and fast multioperations. According to our preliminary evaluation, good performance figures and scalability can be achieved with these techniques in executing parallel programs written with a high-level language and compiled with very early prototype tools.",
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    Forsell, M 2006, 'Scalable general purpose CMP architecture' Paper presented at Scalable Approaches to High-Performance and High-Productivity Computing 2006, ScalPerf'06, Bertinoro, Italy, 3/09/06 - 7/09/06, .

    Scalable general purpose CMP architecture. / Forsell, Martti.

    2006. Paper presented at Scalable Approaches to High-Performance and High-Productivity Computing 2006, ScalPerf'06, Bertinoro, Italy.

    Research output: Contribution to conferenceConference articleScientificpeer-review

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    AB - Due to inherent non-scalability of superscalar processors, processor manufacturers have switched to mul-ti-core or chip multiprocessor (CMP) engines utilizing the symmetrical multiprocessing (SMP) para-digm. Since it is expected that the number of cores per chip will fast increase to a level in which only a fraction of the total computational power can be allocated for a single computational task using SMP, better architectures and computing models with easy-to-use (parallel) programming languages and tools are required. In this presentation we will outline a scalable general purpose CMP architecture being de-veloped at VTT that allows a programmer to utilize fine-grained parallelism under a strong model of computing and to allocate the full computational power of the CMP to arbitrary workloads ranging from a single computational task to multiple independent parallel programs. We will focus on performance is-sues related on latest architectural additions including step cache-based support for concurrect read con-current write (CRCW) access and fast multioperations. According to our preliminary evaluation, good performance figures and scalability can be achieved with these techniques in executing parallel programs written with a high-level language and compiled with very early prototype tools.

    KW - parallel computing

    KW - computer architecture

    KW - scalability

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    Forsell M. Scalable general purpose CMP architecture. 2006. Paper presented at Scalable Approaches to High-Performance and High-Productivity Computing 2006, ScalPerf'06, Bertinoro, Italy.