Sequential Processor Architecture Research at VTT

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific

    Abstract

    In this presentation we will describe transport triggered architecture (TTA) related sequential processor architecture research committed at VTT. The short description and status of our TTA project is given. The advantages and problems of TTA are discussed. Minimal Pipeline Architecture (MPA) is introduced to address the problems of TTA. The results of evaluation of MPA are given. Finally, open research problems are listed.
    Original languageEnglish
    Title of host publicationTTA Workshop Notes 2002
    Subtitle of host publicationTurku, Finland, 7 June 2002
    EditorsJohan Lilius, Seppo Virtanen
    Place of PublicationTurku
    PublisherTurku Centre for Computer Science
    Pages1-29
    ISBN (Print)951-29-2183-9
    Publication statusPublished - 2002
    MoE publication typeB3 Non-refereed article in conference proceedings

    Publication series

    SeriesTUCS General Publications
    Number21
    ISSN1239-1905

    Keywords

    • sequential processor architecture
    • minimal pipeline architecture
    • transport triggered architecture

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  • Cite this

    Forsell, M. (2002). Sequential Processor Architecture Research at VTT. In J. Lilius, & S. Virtanen (Eds.), TTA Workshop Notes 2002: Turku, Finland, 7 June 2002 (pp. 1-29). Turku Centre for Computer Science. TUCS General Publications, No. 21