Shared memory chip multiprocessors supporting strong models of computation: The next wave of general purpose parallel computing?

    Research output: Contribution to conferenceOther conference contributionProfessional

    Abstract

    The arrival multi-core processors or chip multiprocessors (CMP) operated with symmetrical multiprocessing (SMP) has made parallel computing available to the masses. Unfortunately the scalability of the SMP paradigm is poor as the number of processor cores increases. Furthermore, current alternatives to SMP, including non-uniform memory access (NUMA), cache coherent non-uniform memory access (CC-NUMA), vector computing (VEC), and message passing (MP), provide poor performance in general purpose parallel applications and/or programming with them is difficult/tedious. According to recent investigations, an idea from the early 90's - hardware implementation of a strong model of computing, e.g. the Parallel Random Access Machine (PRAM) model, this time on a scalable on-chip distributed shared memory architecture, coupled with the explicit PRAM-driven parallel programming methodology - seem to avoid these problems and therefore opens up an avenue of possibilities in future general purpose parallel computing. In this lecture, we (1) consider shortly the challenges related to on-chip parallel computing, (2) introduce shortly the current CMP paradigms and their problems, (3) introduce the idea of shared memory parallel computing under a strong model of computing, and (4) describe our attempt to realize PRAM computation on a scalable CMP architecture, experimental recursively parallel programming language, and prototype tools for compiling and optimizing programs written with the language for the architecture. Simulation results and programming examples are given.
    Original languageEnglish
    Publication statusPublished - 2008
    MoE publication typeNot Eligible
    EventSeminar on Future Technologies for Shared-Memory Parallel Computing - Ylivieska, Finland
    Duration: 29 Apr 200829 Apr 2008

    Conference

    ConferenceSeminar on Future Technologies for Shared-Memory Parallel Computing
    CountryFinland
    CityYlivieska
    Period29/04/0829/04/08

    Fingerprint

    Parallel processing systems
    Data storage equipment
    Parallel programming
    Memory architecture
    Message passing
    Computer programming languages
    Scalability
    Hardware

    Keywords

    • parallel computing
    • CMP
    • VLSI
    • models of computing
    • PRAM

    Cite this

    Forsell, M. (2008). Shared memory chip multiprocessors supporting strong models of computation: The next wave of general purpose parallel computing?. Seminar on Future Technologies for Shared-Memory Parallel Computing, Ylivieska, Finland.
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    title = "Shared memory chip multiprocessors supporting strong models of computation: The next wave of general purpose parallel computing?",
    abstract = "The arrival multi-core processors or chip multiprocessors (CMP) operated with symmetrical multiprocessing (SMP) has made parallel computing available to the masses. Unfortunately the scalability of the SMP paradigm is poor as the number of processor cores increases. Furthermore, current alternatives to SMP, including non-uniform memory access (NUMA), cache coherent non-uniform memory access (CC-NUMA), vector computing (VEC), and message passing (MP), provide poor performance in general purpose parallel applications and/or programming with them is difficult/tedious. According to recent investigations, an idea from the early 90's - hardware implementation of a strong model of computing, e.g. the Parallel Random Access Machine (PRAM) model, this time on a scalable on-chip distributed shared memory architecture, coupled with the explicit PRAM-driven parallel programming methodology - seem to avoid these problems and therefore opens up an avenue of possibilities in future general purpose parallel computing. In this lecture, we (1) consider shortly the challenges related to on-chip parallel computing, (2) introduce shortly the current CMP paradigms and their problems, (3) introduce the idea of shared memory parallel computing under a strong model of computing, and (4) describe our attempt to realize PRAM computation on a scalable CMP architecture, experimental recursively parallel programming language, and prototype tools for compiling and optimizing programs written with the language for the architecture. Simulation results and programming examples are given.",
    keywords = "parallel computing, CMP, VLSI, models of computing, PRAM",
    author = "Martti Forsell",
    year = "2008",
    language = "English",
    note = "Seminar on Future Technologies for Shared-Memory Parallel Computing ; Conference date: 29-04-2008 Through 29-04-2008",

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    Forsell, M 2008, 'Shared memory chip multiprocessors supporting strong models of computation: The next wave of general purpose parallel computing?', Seminar on Future Technologies for Shared-Memory Parallel Computing, Ylivieska, Finland, 29/04/08 - 29/04/08.

    Shared memory chip multiprocessors supporting strong models of computation : The next wave of general purpose parallel computing? / Forsell, Martti.

    2008. Seminar on Future Technologies for Shared-Memory Parallel Computing, Ylivieska, Finland.

    Research output: Contribution to conferenceOther conference contributionProfessional

    TY - CONF

    T1 - Shared memory chip multiprocessors supporting strong models of computation

    T2 - The next wave of general purpose parallel computing?

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    N2 - The arrival multi-core processors or chip multiprocessors (CMP) operated with symmetrical multiprocessing (SMP) has made parallel computing available to the masses. Unfortunately the scalability of the SMP paradigm is poor as the number of processor cores increases. Furthermore, current alternatives to SMP, including non-uniform memory access (NUMA), cache coherent non-uniform memory access (CC-NUMA), vector computing (VEC), and message passing (MP), provide poor performance in general purpose parallel applications and/or programming with them is difficult/tedious. According to recent investigations, an idea from the early 90's - hardware implementation of a strong model of computing, e.g. the Parallel Random Access Machine (PRAM) model, this time on a scalable on-chip distributed shared memory architecture, coupled with the explicit PRAM-driven parallel programming methodology - seem to avoid these problems and therefore opens up an avenue of possibilities in future general purpose parallel computing. In this lecture, we (1) consider shortly the challenges related to on-chip parallel computing, (2) introduce shortly the current CMP paradigms and their problems, (3) introduce the idea of shared memory parallel computing under a strong model of computing, and (4) describe our attempt to realize PRAM computation on a scalable CMP architecture, experimental recursively parallel programming language, and prototype tools for compiling and optimizing programs written with the language for the architecture. Simulation results and programming examples are given.

    AB - The arrival multi-core processors or chip multiprocessors (CMP) operated with symmetrical multiprocessing (SMP) has made parallel computing available to the masses. Unfortunately the scalability of the SMP paradigm is poor as the number of processor cores increases. Furthermore, current alternatives to SMP, including non-uniform memory access (NUMA), cache coherent non-uniform memory access (CC-NUMA), vector computing (VEC), and message passing (MP), provide poor performance in general purpose parallel applications and/or programming with them is difficult/tedious. According to recent investigations, an idea from the early 90's - hardware implementation of a strong model of computing, e.g. the Parallel Random Access Machine (PRAM) model, this time on a scalable on-chip distributed shared memory architecture, coupled with the explicit PRAM-driven parallel programming methodology - seem to avoid these problems and therefore opens up an avenue of possibilities in future general purpose parallel computing. In this lecture, we (1) consider shortly the challenges related to on-chip parallel computing, (2) introduce shortly the current CMP paradigms and their problems, (3) introduce the idea of shared memory parallel computing under a strong model of computing, and (4) describe our attempt to realize PRAM computation on a scalable CMP architecture, experimental recursively parallel programming language, and prototype tools for compiling and optimizing programs written with the language for the architecture. Simulation results and programming examples are given.

    KW - parallel computing

    KW - CMP

    KW - VLSI

    KW - models of computing

    KW - PRAM

    M3 - Other conference contribution

    ER -

    Forsell M. Shared memory chip multiprocessors supporting strong models of computation: The next wave of general purpose parallel computing?. 2008. Seminar on Future Technologies for Shared-Memory Parallel Computing, Ylivieska, Finland.