Si CMOS platform for quantum information processing

L. Hutin; R. Maurand; D. Kotekar-Patil; A. Corna; Heorhii Bohuslavskyi; X. Jehl; S. Barraud; S. De Franceschi; M. Sanquer; M. Vinet

doi:10.1109/vlsit.2016.7573380

Si CMOS platform for quantum information processing

L. Hutin
, R. Maurand
, D. Kotekar-Patil
, A. Corna
, Heorhii Bohuslavskyi
, X. Jehl
, S. Barraud
, S. De Franceschi
, M. Sanquer
, M. Vinet

Not published at VTT

Laboratoire d'électronique des technologies de l'information (LETI)
Institute for Nanoscience and Cryogenics (INAC)

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself. By demonstrating qubit functionality in a conventional transistor-like layout and process flow, this result bears relevance for the future up-scaling of qubit architectures, including the opportunity of their co-integration with “classical” Si CMOS control circuitry.

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Technology
Publisher	IEEE Institute of Electrical and Electronic Engineers
ISBN (Electronic)	978-1-5090-0638-0
DOIs	https://doi.org/10.1109/vlsit.2016.7573380
Publication status	Published - Jun 2016
MoE publication type	A4 Article in a conference publication

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10.1109/vlsit.2016.7573380

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title = "Si CMOS platform for quantum information processing",

abstract = "We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself. By demonstrating qubit functionality in a conventional transistor-like layout and process flow, this result bears relevance for the future up-scaling of qubit architectures, including the opportunity of their co-integration with “classical” Si CMOS control circuitry.",

author = "L. Hutin and R. Maurand and D. Kotekar-Patil and A. Corna and Heorhii Bohuslavskyi and X. Jehl and S. Barraud and Franceschi, \{S. De\} and M. Sanquer and M. Vinet",

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month = jun,

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language = "English",

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T1 - Si CMOS platform for quantum information processing

AU - Hutin, L.

AU - Maurand, R.

AU - Kotekar-Patil, D.

AU - Corna, A.

AU - Bohuslavskyi, Heorhii

AU - Jehl, X.

AU - Barraud, S.

AU - Franceschi, S. De

AU - Sanquer, M.

AU - Vinet, M.

PY - 2016/6

Y1 - 2016/6

N2 - We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself. By demonstrating qubit functionality in a conventional transistor-like layout and process flow, this result bears relevance for the future up-scaling of qubit architectures, including the opportunity of their co-integration with “classical” Si CMOS control circuitry.

AB - We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself. By demonstrating qubit functionality in a conventional transistor-like layout and process flow, this result bears relevance for the future up-scaling of qubit architectures, including the opportunity of their co-integration with “classical” Si CMOS control circuitry.

U2 - 10.1109/vlsit.2016.7573380

DO - 10.1109/vlsit.2016.7573380

M3 - Conference article in proceedings

BT - 2016 IEEE Symposium on VLSI Technology

PB - IEEE Institute of Electrical and Electronic Engineers

ER -

Si CMOS platform for quantum information processing

Abstract

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