Step caches - a novel approach to concurrent memory access on shared memory MP-SOCs

Matti Forsell

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

11 Citations (Scopus)


In this paper we introduce a novel class of caches, named step caches, that can be used to implement concurrent memory access in shared memory multithreaded multiprocessor systems on chip (MP-SOC) without cache coherency problems. The main difference between ordinary caches and steps caches is that data entered to a step cache is kept valid only until the end of ongoing step of multithreaded execution. We describe the structure and operation of step caches as well as give a performance evaluation of step cache systems with different settings using simple parallel programs on our parametrical MP-SOC framework. According to the evaluation, step caches speed up execution by a factor close to the number of processors in respect to the similar system without step caches and almost achieve the performance of the ideal shared memory systems in plain concurrent access.
Original languageEnglish
Title of host publication2005 NORCHIP
PublisherIEEE Institute of Electrical and Electronic Engineers
ISBN (Print)978-1-4244-0064-5
Publication statusPublished - 2005
MoE publication typeA4 Article in a conference publication
Event23rd Norchip Conference, IEEE NORCHIP 2005 - Oulu, Finland
Duration: 21 Nov 200522 Nov 2005


Conference23rd Norchip Conference, IEEE NORCHIP 2005


  • Concurrent memory access
  • CRCW
  • MP-SOC
  • caches


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