Supporting concurrent memory access in TCF-aware processor architectures

Martti Forsell; Jussi Roivainen; Ville Leppanen; Jesper Larsson Traff

doi:10.1109/NORCHIP.2017.8124962

Supporting concurrent memory access in TCF-aware processor architectures

Martti Forsell, Jussi Roivainen, Ville Leppanen, Jesper Larsson Traff

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

2 Citations (Scopus)

Abstract

The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.

Original language	English
Title of host publication	2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017
Subtitle of host publication	NORCHIP and International Symposium of System-on-Chip, SoC 2017
Publisher	IEEE Institute of Electrical and Electronic Engineers
Number of pages	6
ISBN (Electronic)	978-1-5386-2844-7
ISBN (Print)	978-1-5386-2845-4
DOIs	https://doi.org/10.1109/NORCHIP.2017.8124962
Publication status	Published - 29 Nov 2017
MoE publication type	A4 Article in a conference publication
Event	2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017: NORCHIP and International Symposium of System-on-Chip (SoC) - Linkoping, Sweden Duration: 24 Oct 2017 → 25 Oct 2017

Conference

Conference	2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017
Country/Territory	Sweden
City	Linkoping
Period	24/10/17 → 25/10/17

Keywords

concurrent memory access
parallel computing
processor architecture
programming model
TCF

Access to Document

10.1109/NORCHIP.2017.8124962

Cite this

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title = "Supporting concurrent memory access in TCF-aware processor architectures",

abstract = "The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.",

keywords = "concurrent memory access, parallel computing, processor architecture, programming model, TCF",

author = "Martti Forsell and Jussi Roivainen and Ville Leppanen and Traff, {Jesper Larsson}",

note = "Funding Information: This work was funded by the Academy of Finland grant 289773. Publisher Copyright: {\textcopyright} 2017 IEEE. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.; 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017 : NORCHIP and International Symposium of System-on-Chip (SoC) ; Conference date: 24-10-2017 Through 25-10-2017",

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publisher = "IEEE Institute of Electrical and Electronic Engineers",

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}

Forsell, M , Roivainen, J, Leppanen, V & Traff, JL 2017, Supporting concurrent memory access in TCF-aware processor architectures. in 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017. IEEE Institute of Electrical and Electronic Engineers, 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017, Linkoping, Sweden, 24/10/17. https://doi.org/10.1109/NORCHIP.2017.8124962

Supporting concurrent memory access in TCF-aware processor architectures. / Forsell, Martti ; Roivainen, Jussi; Leppanen, Ville et al.
2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017. IEEE Institute of Electrical and Electronic Engineers, 2017.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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AU - Roivainen, Jussi

AU - Leppanen, Ville

AU - Traff, Jesper Larsson

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Y1 - 2017/11/29

N2 - The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.

AB - The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.

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ER -

Supporting concurrent memory access in TCF-aware processor architectures

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Keywords

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