Supporting concurrent memory access in TCF-aware processor architectures

Martti Forsell, Jussi Roivainen, Ville Leppanen, Jesper Larsson Traff

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

1 Citation (Scopus)

Abstract

The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.

Original languageEnglish
Title of host publication2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017
Subtitle of host publicationNORCHIP and International Symposium of System-on-Chip, SoC 2017, Proceedings
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages1-6
Number of pages6
Volume2017-January
ISBN (Electronic)9781538628447
DOIs
Publication statusPublished - 29 Nov 2017
MoE publication typeA4 Article in a conference publication
Event2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017: NORCHIP and International Symposium of System-on-Chip (SoC) - Linkoping, Sweden
Duration: 24 Oct 201725 Oct 2017

Conference

Conference2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017
CountrySweden
CityLinkoping
Period24/10/1725/10/17

Fingerprint

Flow control
Data storage equipment
Phase structure
Parallel programming
Hardware

Keywords

  • concurrent memory access
  • parallel computing
  • processor architecture
  • programming model
  • TCF

Cite this

Forsell, M., Roivainen, J., Leppanen, V., & Traff, J. L. (2017). Supporting concurrent memory access in TCF-aware processor architectures. In 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017, Proceedings (Vol. 2017-January, pp. 1-6). Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/NORCHIP.2017.8124962
Forsell, Martti ; Roivainen, Jussi ; Leppanen, Ville ; Traff, Jesper Larsson. / Supporting concurrent memory access in TCF-aware processor architectures. 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017, Proceedings. Vol. 2017-January Institute of Electrical and Electronic Engineers IEEE, 2017. pp. 1-6
@inproceedings{1d9b61d10395488da91346bb65127881,
title = "Supporting concurrent memory access in TCF-aware processor architectures",
abstract = "The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.",
keywords = "concurrent memory access, parallel computing, processor architecture, programming model, TCF",
author = "Martti Forsell and Jussi Roivainen and Ville Leppanen and Traff, {Jesper Larsson}",
year = "2017",
month = "11",
day = "29",
doi = "10.1109/NORCHIP.2017.8124962",
language = "English",
volume = "2017-January",
pages = "1--6",
booktitle = "2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017",
publisher = "Institute of Electrical and Electronic Engineers IEEE",
address = "United States",

}

Forsell, M, Roivainen, J, Leppanen, V & Traff, JL 2017, Supporting concurrent memory access in TCF-aware processor architectures. in 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017, Proceedings. vol. 2017-January, Institute of Electrical and Electronic Engineers IEEE, pp. 1-6, 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017, Linkoping, Sweden, 24/10/17. https://doi.org/10.1109/NORCHIP.2017.8124962

Supporting concurrent memory access in TCF-aware processor architectures. / Forsell, Martti; Roivainen, Jussi; Leppanen, Ville; Traff, Jesper Larsson.

2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017, Proceedings. Vol. 2017-January Institute of Electrical and Electronic Engineers IEEE, 2017. p. 1-6.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

TY - GEN

T1 - Supporting concurrent memory access in TCF-aware processor architectures

AU - Forsell, Martti

AU - Roivainen, Jussi

AU - Leppanen, Ville

AU - Traff, Jesper Larsson

PY - 2017/11/29

Y1 - 2017/11/29

N2 - The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.

AB - The Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor.

KW - concurrent memory access

KW - parallel computing

KW - processor architecture

KW - programming model

KW - TCF

UR - http://www.scopus.com/inward/record.url?scp=85045737566&partnerID=8YFLogxK

U2 - 10.1109/NORCHIP.2017.8124962

DO - 10.1109/NORCHIP.2017.8124962

M3 - Conference article in proceedings

VL - 2017-January

SP - 1

EP - 6

BT - 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017

PB - Institute of Electrical and Electronic Engineers IEEE

ER -

Forsell M, Roivainen J, Leppanen V, Traff JL. Supporting concurrent memory access in TCF-aware processor architectures. In 2017 IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip, SoC 2017, Proceedings. Vol. 2017-January. Institute of Electrical and Electronic Engineers IEEE. 2017. p. 1-6 https://doi.org/10.1109/NORCHIP.2017.8124962