Supporting concurrent memory access in TCF processor architectures

Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff

Research output: Contribution to journalArticleScientificpeer-review

Abstract

The Thick Control Flow (TCF) model simplifies parallel programming by bundling computations with the same control flow into single flows of variable thickness, and has the prospect of alleviating redundant usage of software and hardware resources. While architectures that can support the TCF model have been proposed, current proposals cannot support concurrent memory accesses that can both simplify programming and speed up many parallel algorithms by a logarithmic factor. In this paper, we extend current TCF architectures to efficiently support concurrent read as well as write memory accesses. The solution is based on bounded size step-caches, and exploit the two-part, hybrid, frontend-backend structure of current TCF processors, and synchronization properties of the TCF model itself. According to our simulation-based evaluation, a concurrent memory access TCF processor with B backends can execute algorithms with substantial concurrent memory accesses up to B times faster than a baseline TCF processor not supporting concurrent memory access. The hardware overhead of the solution is estimated to be modest. We include parallel program code to illustrate the gains by supporting concurrent memory accesses.

Original languageEnglish
Pages (from-to)226-236
Number of pages11
JournalMicroprocessors and Microsystems
Volume63
DOIs
Publication statusPublished - 1 Nov 2018
MoE publication typeNot Eligible

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Flow control
Data storage equipment
Parallel programming
Computer programming
Parallel algorithms
Computer hardware
Synchronization
Hardware

Keywords

  • Concurrent memory access
  • Parallel computing
  • Processor architecture
  • Programming model
  • TCF

Cite this

@article{bec5a6a53cda41e791df9976424851e9,
title = "Supporting concurrent memory access in TCF processor architectures",
abstract = "The Thick Control Flow (TCF) model simplifies parallel programming by bundling computations with the same control flow into single flows of variable thickness, and has the prospect of alleviating redundant usage of software and hardware resources. While architectures that can support the TCF model have been proposed, current proposals cannot support concurrent memory accesses that can both simplify programming and speed up many parallel algorithms by a logarithmic factor. In this paper, we extend current TCF architectures to efficiently support concurrent read as well as write memory accesses. The solution is based on bounded size step-caches, and exploit the two-part, hybrid, frontend-backend structure of current TCF processors, and synchronization properties of the TCF model itself. According to our simulation-based evaluation, a concurrent memory access TCF processor with B backends can execute algorithms with substantial concurrent memory accesses up to B times faster than a baseline TCF processor not supporting concurrent memory access. The hardware overhead of the solution is estimated to be modest. We include parallel program code to illustrate the gains by supporting concurrent memory accesses.",
keywords = "Concurrent memory access, Parallel computing, Processor architecture, Programming model, TCF",
author = "Martti Forsell and Jussi Roivainen and Ville Lepp{\"a}nen and Tr{\"a}ff, {Jesper Larsson}",
year = "2018",
month = "11",
day = "1",
doi = "10.1016/j.micpro.2018.09.013",
language = "English",
volume = "63",
pages = "226--236",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",

}

Supporting concurrent memory access in TCF processor architectures. / Forsell, Martti; Roivainen, Jussi; Leppänen, Ville; Träff, Jesper Larsson.

In: Microprocessors and Microsystems, Vol. 63, 01.11.2018, p. 226-236.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - Supporting concurrent memory access in TCF processor architectures

AU - Forsell, Martti

AU - Roivainen, Jussi

AU - Leppänen, Ville

AU - Träff, Jesper Larsson

PY - 2018/11/1

Y1 - 2018/11/1

N2 - The Thick Control Flow (TCF) model simplifies parallel programming by bundling computations with the same control flow into single flows of variable thickness, and has the prospect of alleviating redundant usage of software and hardware resources. While architectures that can support the TCF model have been proposed, current proposals cannot support concurrent memory accesses that can both simplify programming and speed up many parallel algorithms by a logarithmic factor. In this paper, we extend current TCF architectures to efficiently support concurrent read as well as write memory accesses. The solution is based on bounded size step-caches, and exploit the two-part, hybrid, frontend-backend structure of current TCF processors, and synchronization properties of the TCF model itself. According to our simulation-based evaluation, a concurrent memory access TCF processor with B backends can execute algorithms with substantial concurrent memory accesses up to B times faster than a baseline TCF processor not supporting concurrent memory access. The hardware overhead of the solution is estimated to be modest. We include parallel program code to illustrate the gains by supporting concurrent memory accesses.

AB - The Thick Control Flow (TCF) model simplifies parallel programming by bundling computations with the same control flow into single flows of variable thickness, and has the prospect of alleviating redundant usage of software and hardware resources. While architectures that can support the TCF model have been proposed, current proposals cannot support concurrent memory accesses that can both simplify programming and speed up many parallel algorithms by a logarithmic factor. In this paper, we extend current TCF architectures to efficiently support concurrent read as well as write memory accesses. The solution is based on bounded size step-caches, and exploit the two-part, hybrid, frontend-backend structure of current TCF processors, and synchronization properties of the TCF model itself. According to our simulation-based evaluation, a concurrent memory access TCF processor with B backends can execute algorithms with substantial concurrent memory accesses up to B times faster than a baseline TCF processor not supporting concurrent memory access. The hardware overhead of the solution is estimated to be modest. We include parallel program code to illustrate the gains by supporting concurrent memory accesses.

KW - Concurrent memory access

KW - Parallel computing

KW - Processor architecture

KW - Programming model

KW - TCF

UR - http://www.scopus.com/inward/record.url?scp=85054190193&partnerID=8YFLogxK

U2 - 10.1016/j.micpro.2018.09.013

DO - 10.1016/j.micpro.2018.09.013

M3 - Article

AN - SCOPUS:85054190193

VL - 63

SP - 226

EP - 236

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

ER -